0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
0004 *
0005 * Copyright (C) 2013 Texas Instruments, Inc.
0006 */
0007 &prm_clocks {
0008 corex2_d3_fck: corex2_d3_fck {
0009 #clock-cells = <0>;
0010 compatible = "fixed-factor-clock";
0011 clocks = <&corex2_fck>;
0012 clock-mult = <1>;
0013 clock-div = <3>;
0014 };
0015
0016 corex2_d5_fck: corex2_d5_fck {
0017 #clock-cells = <0>;
0018 compatible = "fixed-factor-clock";
0019 clocks = <&corex2_fck>;
0020 clock-mult = <1>;
0021 clock-div = <5>;
0022 };
0023 };
0024 &cm_clocks {
0025 dpll5_ck: dpll5_ck@d04 {
0026 #clock-cells = <0>;
0027 compatible = "ti,omap3-dpll-clock";
0028 clocks = <&sys_ck>, <&sys_ck>;
0029 reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
0030 ti,low-power-stop;
0031 ti,lock;
0032 };
0033
0034 dpll5_m2_ck: dpll5_m2_ck@d50 {
0035 #clock-cells = <0>;
0036 compatible = "ti,divider-clock";
0037 clocks = <&dpll5_ck>;
0038 ti,max-div = <31>;
0039 reg = <0x0d50>;
0040 ti,index-starts-at-one;
0041 };
0042
0043 sgx_gate_fck: sgx_gate_fck@b00 {
0044 #clock-cells = <0>;
0045 compatible = "ti,composite-gate-clock";
0046 clocks = <&core_ck>;
0047 ti,bit-shift = <1>;
0048 reg = <0x0b00>;
0049 };
0050
0051 core_d3_ck: core_d3_ck {
0052 #clock-cells = <0>;
0053 compatible = "fixed-factor-clock";
0054 clocks = <&core_ck>;
0055 clock-mult = <1>;
0056 clock-div = <3>;
0057 };
0058
0059 core_d4_ck: core_d4_ck {
0060 #clock-cells = <0>;
0061 compatible = "fixed-factor-clock";
0062 clocks = <&core_ck>;
0063 clock-mult = <1>;
0064 clock-div = <4>;
0065 };
0066
0067 core_d6_ck: core_d6_ck {
0068 #clock-cells = <0>;
0069 compatible = "fixed-factor-clock";
0070 clocks = <&core_ck>;
0071 clock-mult = <1>;
0072 clock-div = <6>;
0073 };
0074
0075 omap_192m_alwon_fck: omap_192m_alwon_fck {
0076 #clock-cells = <0>;
0077 compatible = "fixed-factor-clock";
0078 clocks = <&dpll4_m2x2_ck>;
0079 clock-mult = <1>;
0080 clock-div = <1>;
0081 };
0082
0083 core_d2_ck: core_d2_ck {
0084 #clock-cells = <0>;
0085 compatible = "fixed-factor-clock";
0086 clocks = <&core_ck>;
0087 clock-mult = <1>;
0088 clock-div = <2>;
0089 };
0090
0091 sgx_mux_fck: sgx_mux_fck@b40 {
0092 #clock-cells = <0>;
0093 compatible = "ti,composite-mux-clock";
0094 clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
0095 reg = <0x0b40>;
0096 };
0097
0098 sgx_fck: sgx_fck {
0099 #clock-cells = <0>;
0100 compatible = "ti,composite-clock";
0101 clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
0102 };
0103
0104 sgx_ick: sgx_ick@b10 {
0105 #clock-cells = <0>;
0106 compatible = "ti,wait-gate-clock";
0107 clocks = <&l3_ick>;
0108 reg = <0x0b10>;
0109 ti,bit-shift = <0>;
0110 };
0111
0112 cpefuse_fck: cpefuse_fck@a08 {
0113 #clock-cells = <0>;
0114 compatible = "ti,gate-clock";
0115 clocks = <&sys_ck>;
0116 reg = <0x0a08>;
0117 ti,bit-shift = <0>;
0118 };
0119
0120 ts_fck: ts_fck@a08 {
0121 #clock-cells = <0>;
0122 compatible = "ti,gate-clock";
0123 clocks = <&omap_32k_fck>;
0124 reg = <0x0a08>;
0125 ti,bit-shift = <1>;
0126 };
0127
0128 usbtll_fck: usbtll_fck@a08 {
0129 #clock-cells = <0>;
0130 compatible = "ti,wait-gate-clock";
0131 clocks = <&dpll5_m2_ck>;
0132 reg = <0x0a08>;
0133 ti,bit-shift = <2>;
0134 };
0135
0136 /* CM_ICLKEN3_CORE */
0137 clock@a18 {
0138 compatible = "ti,clksel";
0139 reg = <0xa18>;
0140 #clock-cells = <2>;
0141 #address-cells = <0>;
0142
0143 usbtll_ick: clock-usbtll-ick {
0144 #clock-cells = <0>;
0145 compatible = "ti,omap3-interface-clock";
0146 clock-output-names = "usbtll_ick";
0147 clocks = <&core_l4_ick>;
0148 ti,bit-shift = <2>;
0149 };
0150 };
0151
0152 clock@a10 {
0153 compatible = "ti,clksel";
0154 reg = <0xa10>;
0155 #clock-cells = <2>;
0156 #address-cells = <0>;
0157
0158 mmchs3_ick: clock-mmchs3-ick {
0159 #clock-cells = <0>;
0160 compatible = "ti,omap3-interface-clock";
0161 clock-output-names = "mmchs3_ick";
0162 clocks = <&core_l4_ick>;
0163 ti,bit-shift = <30>;
0164 };
0165 };
0166
0167 clock@a00 {
0168 compatible = "ti,clksel";
0169 reg = <0xa00>;
0170 #clock-cells = <2>;
0171 #address-cells = <0>;
0172
0173 mmchs3_fck: clock-mmchs3-fck {
0174 #clock-cells = <0>;
0175 compatible = "ti,wait-gate-clock";
0176 clock-output-names = "mmchs3_fck";
0177 clocks = <&core_96m_fck>;
0178 ti,bit-shift = <30>;
0179 };
0180 };
0181
0182 clock@e00 {
0183 compatible = "ti,clksel";
0184 reg = <0xe00>;
0185 #clock-cells = <2>;
0186 #address-cells = <0>;
0187
0188 dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 {
0189 #clock-cells = <0>;
0190 compatible = "ti,dss-gate-clock";
0191 clock-output-names = "dss1_alwon_fck_3430es2";
0192 clocks = <&dpll4_m4x2_ck>;
0193 ti,bit-shift = <0>;
0194 ti,set-rate-parent;
0195 };
0196 };
0197
0198 dss_ick: dss_ick_3430es2@e10 {
0199 #clock-cells = <0>;
0200 compatible = "ti,omap3-dss-interface-clock";
0201 clocks = <&l4_ick>;
0202 reg = <0x0e10>;
0203 ti,bit-shift = <0>;
0204 };
0205
0206 usbhost_120m_fck: usbhost_120m_fck@1400 {
0207 #clock-cells = <0>;
0208 compatible = "ti,gate-clock";
0209 clocks = <&dpll5_m2_ck>;
0210 reg = <0x1400>;
0211 ti,bit-shift = <1>;
0212 };
0213
0214 usbhost_48m_fck: usbhost_48m_fck@1400 {
0215 #clock-cells = <0>;
0216 compatible = "ti,dss-gate-clock";
0217 clocks = <&omap_48m_fck>;
0218 reg = <0x1400>;
0219 ti,bit-shift = <0>;
0220 };
0221
0222 usbhost_ick: usbhost_ick@1410 {
0223 #clock-cells = <0>;
0224 compatible = "ti,omap3-dss-interface-clock";
0225 clocks = <&l4_ick>;
0226 reg = <0x1410>;
0227 ti,bit-shift = <0>;
0228 };
0229 };
0230
0231 &cm_clockdomains {
0232 dpll5_clkdm: dpll5_clkdm {
0233 compatible = "ti,clockdomain";
0234 clocks = <&dpll5_ck>;
0235 };
0236
0237 sgx_clkdm: sgx_clkdm {
0238 compatible = "ti,clockdomain";
0239 clocks = <&sgx_ick>;
0240 };
0241
0242 dss_clkdm: dss_clkdm {
0243 compatible = "ti,clockdomain";
0244 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
0245 <&dss1_alwon_fck>, <&dss_ick>;
0246 };
0247
0248 core_l4_clkdm: core_l4_clkdm {
0249 compatible = "ti,clockdomain";
0250 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
0251 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
0252 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
0253 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
0254 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
0255 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
0256 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
0257 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
0258 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
0259 <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
0260 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
0261 };
0262
0263 usbhost_clkdm: usbhost_clkdm {
0264 compatible = "ti,clockdomain";
0265 clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
0266 <&usbhost_ick>;
0267 };
0268 };
