0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for OMAP34xx/OMAP35xx SoC
0004 *
0005 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 #include <dt-bindings/bus/ti-sysc.h>
0009 #include <dt-bindings/media/omap3-isp.h>
0010
0011 #include "omap3.dtsi"
0012
0013 / {
0014 cpus {
0015 cpu: cpu@0 {
0016 /* OMAP343x/OMAP35xx variants OPP1-6 */
0017 operating-points-v2 = <&cpu0_opp_table>;
0018
0019 clock-latency = <300000>; /* From legacy driver */
0020 #cooling-cells = <2>;
0021 };
0022 };
0023
0024 cpu0_opp_table: opp-table {
0025 compatible = "operating-points-v2-ti-cpu";
0026 syscon = <&scm_conf>;
0027
0028 opp1-125000000 {
0029 opp-hz = /bits/ 64 <125000000>;
0030 /*
0031 * we currently only select the max voltage from table
0032 * Table 3-3 of the omap3530 Data sheet (SPRS507F).
0033 * Format is: <target min max>
0034 */
0035 opp-microvolt = <975000 975000 975000>;
0036 /*
0037 * first value is silicon revision bit mask
0038 * second one 720MHz Device Identification bit mask
0039 */
0040 opp-supported-hw = <0xffffffff 3>;
0041 };
0042
0043 opp2-250000000 {
0044 opp-hz = /bits/ 64 <250000000>;
0045 opp-microvolt = <1075000 1075000 1075000>;
0046 opp-supported-hw = <0xffffffff 3>;
0047 opp-suspend;
0048 };
0049
0050 opp3-500000000 {
0051 opp-hz = /bits/ 64 <500000000>;
0052 opp-microvolt = <1200000 1200000 1200000>;
0053 opp-supported-hw = <0xffffffff 3>;
0054 };
0055
0056 opp4-550000000 {
0057 opp-hz = /bits/ 64 <550000000>;
0058 opp-microvolt = <1275000 1275000 1275000>;
0059 opp-supported-hw = <0xffffffff 3>;
0060 };
0061
0062 opp5-600000000 {
0063 opp-hz = /bits/ 64 <600000000>;
0064 opp-microvolt = <1350000 1350000 1350000>;
0065 opp-supported-hw = <0xffffffff 3>;
0066 };
0067
0068 opp6-720000000 {
0069 opp-hz = /bits/ 64 <720000000>;
0070 opp-microvolt = <1350000 1350000 1350000>;
0071 /* only high-speed grade omap3530 devices */
0072 opp-supported-hw = <0xffffffff 2>;
0073 turbo-mode;
0074 };
0075 };
0076
0077 ocp@68000000 {
0078 omap3_pmx_core2: pinmux@480025d8 {
0079 compatible = "ti,omap3-padconf", "pinctrl-single";
0080 reg = <0x480025d8 0x24>;
0081 #address-cells = <1>;
0082 #size-cells = <0>;
0083 #pinctrl-cells = <1>;
0084 #interrupt-cells = <1>;
0085 interrupt-controller;
0086 pinctrl-single,register-width = <16>;
0087 pinctrl-single,function-mask = <0xff1f>;
0088 };
0089
0090 isp: isp@480bc000 {
0091 compatible = "ti,omap3-isp";
0092 reg = <0x480bc000 0x12fc
0093 0x480bd800 0x017c>;
0094 interrupts = <24>;
0095 iommus = <&mmu_isp>;
0096 syscon = <&scm_conf 0x6c>;
0097 ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
0098 #clock-cells = <1>;
0099 ports {
0100 #address-cells = <1>;
0101 #size-cells = <0>;
0102 };
0103 };
0104
0105 bandgap: bandgap@48002524 {
0106 reg = <0x48002524 0x4>;
0107 compatible = "ti,omap34xx-bandgap";
0108 #thermal-sensor-cells = <0>;
0109 };
0110
0111 target-module@480cb000 {
0112 compatible = "ti,sysc-omap3430-sr", "ti,sysc";
0113 ti,hwmods = "smartreflex_core";
0114 reg = <0x480cb024 0x4>;
0115 reg-names = "sysc";
0116 ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
0117 clocks = <&sr2_fck>;
0118 clock-names = "fck";
0119 #address-cells = <1>;
0120 #size-cells = <1>;
0121 ranges = <0 0x480cb000 0x001000>;
0122
0123 smartreflex_core: smartreflex@0 {
0124 compatible = "ti,omap3-smartreflex-core";
0125 reg = <0 0x400>;
0126 interrupts = <19>;
0127 };
0128 };
0129
0130 target-module@480c9000 {
0131 compatible = "ti,sysc-omap3430-sr", "ti,sysc";
0132 ti,hwmods = "smartreflex_mpu_iva";
0133 reg = <0x480c9024 0x4>;
0134 reg-names = "sysc";
0135 ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
0136 clocks = <&sr1_fck>;
0137 clock-names = "fck";
0138 #address-cells = <1>;
0139 #size-cells = <1>;
0140 ranges = <0 0x480c9000 0x001000>;
0141
0142 smartreflex_mpu_iva: smartreflex@480c9000 {
0143 compatible = "ti,omap3-smartreflex-mpu-iva";
0144 reg = <0 0x400>;
0145 interrupts = <18>;
0146 };
0147 };
0148
0149 /*
0150 * On omap34xx the OCP registers do not seem to be accessible
0151 * at all unlike on 36xx. Maybe SGX is permanently set to
0152 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
0153 * write-only at 0x50000e10. We detect SGX based on the SGX
0154 * revision register instead of the unreadable OCP revision
0155 * register. Also note that on early 34xx es1 revision there
0156 * are also different clocks, but we do not have any dts users
0157 * for it.
0158 */
0159 sgx_module: target-module@50000000 {
0160 compatible = "ti,sysc-omap2", "ti,sysc";
0161 reg = <0x50000014 0x4>;
0162 reg-names = "rev";
0163 clocks = <&sgx_fck>, <&sgx_ick>;
0164 clock-names = "fck", "ick";
0165 #address-cells = <1>;
0166 #size-cells = <1>;
0167 ranges = <0 0x50000000 0x4000>;
0168
0169 /*
0170 * Closed source PowerVR driver, no child device
0171 * binding or driver in mainline
0172 */
0173 };
0174 };
0175
0176 thermal_zones: thermal-zones {
0177 #include "omap3-cpu-thermal.dtsi"
0178 };
0179 };
0180
0181 &ssi {
0182 status = "okay";
0183
0184 clocks = <&ssi_ssr_fck>,
0185 <&ssi_sst_fck>,
0186 <&ssi_ick>;
0187 clock-names = "ssi_ssr_fck",
0188 "ssi_sst_fck",
0189 "ssi_ick";
0190 };
0191
0192 /include/ "omap34xx-omap36xx-clocks.dtsi"
0193 /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
0194 /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
