0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for OMAP34XX/OMAP36XX clock data
0004 *
0005 * Copyright (C) 2013 Texas Instruments, Inc.
0006 */
0007 &cm_clocks {
0008 security_l4_ick2: security_l4_ick2 {
0009 #clock-cells = <0>;
0010 compatible = "fixed-factor-clock";
0011 clocks = <&l4_ick>;
0012 clock-mult = <1>;
0013 clock-div = <1>;
0014 };
0015
0016 clock@a14 {
0017 compatible = "ti,clksel";
0018 reg = <0xa14>;
0019 #clock-cells = <2>;
0020 #address-cells = <0>;
0021
0022 aes1_ick: clock-aes1-ick {
0023 #clock-cells = <0>;
0024 compatible = "ti,omap3-interface-clock";
0025 clock-output-names = "aes1_ick";
0026 clocks = <&security_l4_ick2>;
0027 ti,bit-shift = <3>;
0028 };
0029
0030 rng_ick: clock-rng-ick {
0031 #clock-cells = <0>;
0032 compatible = "ti,omap3-interface-clock";
0033 clock-output-names = "rng_ick";
0034 clocks = <&security_l4_ick2>;
0035 ti,bit-shift = <2>;
0036 };
0037
0038 sha11_ick: clock-sha11-ick {
0039 #clock-cells = <0>;
0040 compatible = "ti,omap3-interface-clock";
0041 clock-output-names = "sha11_ick";
0042 clocks = <&security_l4_ick2>;
0043 ti,bit-shift = <1>;
0044 };
0045
0046 des1_ick: clock-des1-ick {
0047 #clock-cells = <0>;
0048 compatible = "ti,omap3-interface-clock";
0049 clock-output-names = "des1_ick";
0050 clocks = <&security_l4_ick2>;
0051 ti,bit-shift = <0>;
0052 };
0053
0054 pka_ick: clock-pka-ick {
0055 #clock-cells = <0>;
0056 compatible = "ti,omap3-interface-clock";
0057 clock-output-names = "pka_ick";
0058 clocks = <&security_l3_ick>;
0059 ti,bit-shift = <4>;
0060 };
0061 };
0062
0063 /* CM_FCLKEN_CAM */
0064 clock@f00 {
0065 compatible = "ti,clksel";
0066 reg = <0xf00>;
0067 #clock-cells = <2>;
0068 #address-cells = <0>;
0069
0070 cam_mclk: clock-cam-mclk {
0071 #clock-cells = <0>;
0072 compatible = "ti,gate-clock";
0073 clock-output-names = "cam_mclk";
0074 clocks = <&dpll4_m5x2_ck>;
0075 ti,bit-shift = <0>;
0076 ti,set-rate-parent;
0077 };
0078
0079 csi2_96m_fck: clock-csi2-96m-fck {
0080 #clock-cells = <0>;
0081 compatible = "ti,gate-clock";
0082 clock-output-names = "csi2_96m_fck";
0083 clocks = <&core_96m_fck>;
0084 ti,bit-shift = <1>;
0085 };
0086 };
0087
0088 cam_ick: cam_ick@f10 {
0089 #clock-cells = <0>;
0090 compatible = "ti,omap3-no-wait-interface-clock";
0091 clocks = <&l4_ick>;
0092 reg = <0x0f10>;
0093 ti,bit-shift = <0>;
0094 };
0095
0096 security_l3_ick: security_l3_ick {
0097 #clock-cells = <0>;
0098 compatible = "fixed-factor-clock";
0099 clocks = <&l3_ick>;
0100 clock-mult = <1>;
0101 clock-div = <1>;
0102 };
0103
0104 clock@a10 {
0105 compatible = "ti,clksel";
0106 reg = <0xa10>;
0107 #clock-cells = <2>;
0108 #address-cells = <0>;
0109
0110 icr_ick: clock-icr-ick {
0111 #clock-cells = <0>;
0112 compatible = "ti,omap3-interface-clock";
0113 clock-output-names = "icr_ick";
0114 clocks = <&core_l4_ick>;
0115 ti,bit-shift = <29>;
0116 };
0117
0118 des2_ick: clock-des2-ick {
0119 #clock-cells = <0>;
0120 compatible = "ti,omap3-interface-clock";
0121 clock-output-names = "des2_ick";
0122 clocks = <&core_l4_ick>;
0123 ti,bit-shift = <26>;
0124 };
0125
0126 mspro_ick: clock-mspro-ick {
0127 #clock-cells = <0>;
0128 compatible = "ti,omap3-interface-clock";
0129 clock-output-names = "mspro_ick";
0130 clocks = <&core_l4_ick>;
0131 ti,bit-shift = <23>;
0132 };
0133
0134 mailboxes_ick: clock-mailboxes-ick {
0135 #clock-cells = <0>;
0136 compatible = "ti,omap3-interface-clock";
0137 clock-output-names = "mailboxes_ick";
0138 clocks = <&core_l4_ick>;
0139 ti,bit-shift = <7>;
0140 };
0141
0142 sad2d_ick: clock-sad2d-ick {
0143 #clock-cells = <0>;
0144 compatible = "ti,omap3-interface-clock";
0145 clock-output-names = "sad2d_ick";
0146 clocks = <&l3_ick>;
0147 ti,bit-shift = <3>;
0148 };
0149 };
0150
0151 ssi_l4_ick: ssi_l4_ick {
0152 #clock-cells = <0>;
0153 compatible = "fixed-factor-clock";
0154 clocks = <&l4_ick>;
0155 clock-mult = <1>;
0156 clock-div = <1>;
0157 };
0158
0159 clock@c00 {
0160 compatible = "ti,clksel";
0161 reg = <0xc00>;
0162 #clock-cells = <2>;
0163 #address-cells = <0>;
0164
0165 sr1_fck: clock-sr1-fck {
0166 #clock-cells = <0>;
0167 compatible = "ti,wait-gate-clock";
0168 clock-output-names = "sr1_fck";
0169 clocks = <&sys_ck>;
0170 ti,bit-shift = <6>;
0171 };
0172
0173 sr2_fck: clock-sr2-fck {
0174 #clock-cells = <0>;
0175 compatible = "ti,wait-gate-clock";
0176 clock-output-names = "sr2_fck";
0177 clocks = <&sys_ck>;
0178 ti,bit-shift = <7>;
0179 };
0180 };
0181
0182 sr_l4_ick: sr_l4_ick {
0183 #clock-cells = <0>;
0184 compatible = "fixed-factor-clock";
0185 clocks = <&l4_ick>;
0186 clock-mult = <1>;
0187 clock-div = <1>;
0188 };
0189
0190 dpll2_fck: dpll2_fck@40 {
0191 #clock-cells = <0>;
0192 compatible = "ti,divider-clock";
0193 clocks = <&core_ck>;
0194 ti,bit-shift = <19>;
0195 ti,max-div = <7>;
0196 reg = <0x0040>;
0197 ti,index-starts-at-one;
0198 };
0199
0200 dpll2_ck: dpll2_ck@4 {
0201 #clock-cells = <0>;
0202 compatible = "ti,omap3-dpll-clock";
0203 clocks = <&sys_ck>, <&dpll2_fck>;
0204 reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
0205 ti,low-power-stop;
0206 ti,lock;
0207 ti,low-power-bypass;
0208 };
0209
0210 dpll2_m2_ck: dpll2_m2_ck@44 {
0211 #clock-cells = <0>;
0212 compatible = "ti,divider-clock";
0213 clocks = <&dpll2_ck>;
0214 ti,max-div = <31>;
0215 reg = <0x0044>;
0216 ti,index-starts-at-one;
0217 };
0218
0219 iva2_ck: iva2_ck@0 {
0220 #clock-cells = <0>;
0221 compatible = "ti,wait-gate-clock";
0222 clocks = <&dpll2_m2_ck>;
0223 reg = <0x0000>;
0224 ti,bit-shift = <0>;
0225 };
0226
0227 clock@a00 {
0228 compatible = "ti,clksel";
0229 reg = <0xa00>;
0230 #clock-cells = <2>;
0231 #address-cells = <0>;
0232
0233 modem_fck: clock-modem-fck {
0234 #clock-cells = <0>;
0235 compatible = "ti,omap3-interface-clock";
0236 clock-output-names = "modem_fck";
0237 clocks = <&sys_ck>;
0238 ti,bit-shift = <31>;
0239 };
0240
0241 mspro_fck: clock-mspro-fck {
0242 #clock-cells = <0>;
0243 compatible = "ti,wait-gate-clock";
0244 clock-output-names = "mspro_fck";
0245 clocks = <&core_96m_fck>;
0246 ti,bit-shift = <23>;
0247 };
0248 };
0249
0250 /* CM_ICLKEN3_CORE */
0251 clock@a18 {
0252 compatible = "ti,clksel";
0253 reg = <0xa18>;
0254 #clock-cells = <2>;
0255 #address-cells = <0>;
0256
0257 mad2d_ick: clock-mad2d-ick {
0258 #clock-cells = <0>;
0259 compatible = "ti,omap3-interface-clock";
0260 clock-output-names = "mad2d_ick";
0261 clocks = <&l3_ick>;
0262 ti,bit-shift = <3>;
0263 };
0264 };
0265
0266 };
0267
0268 &cm_clockdomains {
0269 cam_clkdm: cam_clkdm {
0270 compatible = "ti,clockdomain";
0271 clocks = <&cam_ick>, <&csi2_96m_fck>;
0272 };
0273
0274 iva2_clkdm: iva2_clkdm {
0275 compatible = "ti,clockdomain";
0276 clocks = <&iva2_ck>;
0277 };
0278
0279 dpll2_clkdm: dpll2_clkdm {
0280 compatible = "ti,clockdomain";
0281 clocks = <&dpll2_ck>;
0282 };
0283
0284 wkup_clkdm: wkup_clkdm {
0285 compatible = "ti,clockdomain";
0286 clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
0287 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
0288 <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
0289 };
0290
0291 d2d_clkdm: d2d_clkdm {
0292 compatible = "ti,clockdomain";
0293 clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
0294 };
0295
0296 core_l4_clkdm: core_l4_clkdm {
0297 compatible = "ti,clockdomain";
0298 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
0299 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
0300 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
0301 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
0302 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
0303 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
0304 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
0305 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
0306 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
0307 <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
0308 <&rng_ick>, <&mspro_fck>;
0309 };
0310 };
