0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for OMAP3430 ES1 clock data
0004 *
0005 * Copyright (C) 2013 Texas Instruments, Inc.
0006 */
0007 &cm_clocks {
0008 gfx_l3_ck: gfx_l3_ck@b10 {
0009 #clock-cells = <0>;
0010 compatible = "ti,wait-gate-clock";
0011 clocks = <&l3_ick>;
0012 reg = <0x0b10>;
0013 ti,bit-shift = <0>;
0014 };
0015
0016 gfx_l3_fck: gfx_l3_fck@b40 {
0017 #clock-cells = <0>;
0018 compatible = "ti,divider-clock";
0019 clocks = <&l3_ick>;
0020 ti,max-div = <7>;
0021 reg = <0x0b40>;
0022 ti,index-starts-at-one;
0023 };
0024
0025 gfx_l3_ick: gfx_l3_ick {
0026 #clock-cells = <0>;
0027 compatible = "fixed-factor-clock";
0028 clocks = <&gfx_l3_ck>;
0029 clock-mult = <1>;
0030 clock-div = <1>;
0031 };
0032
0033 gfx_cg1_ck: gfx_cg1_ck@b00 {
0034 #clock-cells = <0>;
0035 compatible = "ti,wait-gate-clock";
0036 clocks = <&gfx_l3_fck>;
0037 reg = <0x0b00>;
0038 ti,bit-shift = <1>;
0039 };
0040
0041 gfx_cg2_ck: gfx_cg2_ck@b00 {
0042 #clock-cells = <0>;
0043 compatible = "ti,wait-gate-clock";
0044 clocks = <&gfx_l3_fck>;
0045 reg = <0x0b00>;
0046 ti,bit-shift = <2>;
0047 };
0048
0049 clock@a00 {
0050 compatible = "ti,clksel";
0051 reg = <0xa00>;
0052 #clock-cells = <2>;
0053 #address-cells = <0>;
0054
0055 d2d_26m_fck: clock-d2d-26m-fck {
0056 #clock-cells = <0>;
0057 compatible = "ti,wait-gate-clock";
0058 clock-output-names = "d2d_26m_fck";
0059 clocks = <&sys_ck>;
0060 ti,bit-shift = <3>;
0061 };
0062
0063 fshostusb_fck: clock-fshostusb-fck {
0064 #clock-cells = <0>;
0065 compatible = "ti,wait-gate-clock";
0066 clock-output-names = "fshostusb_fck";
0067 clocks = <&core_48m_fck>;
0068 ti,bit-shift = <5>;
0069 };
0070
0071 ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 {
0072 #clock-cells = <0>;
0073 compatible = "ti,composite-no-wait-gate-clock";
0074 clock-output-names = "ssi_ssr_gate_fck_3430es1";
0075 clocks = <&corex2_fck>;
0076 ti,bit-shift = <0>;
0077 };
0078 };
0079
0080 clock@a40 {
0081 compatible = "ti,clksel";
0082 reg = <0xa40>;
0083 #clock-cells = <2>;
0084 #address-cells = <0>;
0085
0086 ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 {
0087 #clock-cells = <0>;
0088 compatible = "ti,composite-divider-clock";
0089 clock-output-names = "ssi_ssr_div_fck_3430es1";
0090 clocks = <&corex2_fck>;
0091 ti,bit-shift = <8>;
0092 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
0093 };
0094
0095 usb_l4_div_ick: clock-usb-l4-div-ick {
0096 #clock-cells = <0>;
0097 compatible = "ti,composite-divider-clock";
0098 clock-output-names = "usb_l4_div_ick";
0099 clocks = <&l4_ick>;
0100 ti,bit-shift = <4>;
0101 ti,max-div = <1>;
0102 ti,index-starts-at-one;
0103 };
0104 };
0105
0106 ssi_ssr_fck: ssi_ssr_fck_3430es1 {
0107 #clock-cells = <0>;
0108 compatible = "ti,composite-clock";
0109 clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
0110 };
0111
0112 ssi_sst_fck: ssi_sst_fck_3430es1 {
0113 #clock-cells = <0>;
0114 compatible = "fixed-factor-clock";
0115 clocks = <&ssi_ssr_fck>;
0116 clock-mult = <1>;
0117 clock-div = <2>;
0118 };
0119
0120 clock@a10 {
0121 compatible = "ti,clksel";
0122 reg = <0xa10>;
0123 #clock-cells = <2>;
0124 #address-cells = <0>;
0125
0126 hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1 {
0127 #clock-cells = <0>;
0128 compatible = "ti,omap3-no-wait-interface-clock";
0129 clock-output-names = "hsotgusb_ick_3430es1";
0130 clocks = <&core_l3_ick>;
0131 ti,bit-shift = <4>;
0132 };
0133
0134 fac_ick: clock-fac-ick {
0135 #clock-cells = <0>;
0136 compatible = "ti,omap3-interface-clock";
0137 clock-output-names = "fac_ick";
0138 clocks = <&core_l4_ick>;
0139 ti,bit-shift = <8>;
0140 };
0141
0142 ssi_ick: clock-ssi-ick-3430es1 {
0143 #clock-cells = <0>;
0144 compatible = "ti,omap3-no-wait-interface-clock";
0145 clock-output-names = "ssi_ick_3430es1";
0146 clocks = <&ssi_l4_ick>;
0147 ti,bit-shift = <0>;
0148 };
0149
0150 usb_l4_gate_ick: clock-usb-l4-gate-ick {
0151 #clock-cells = <0>;
0152 compatible = "ti,composite-interface-clock";
0153 clock-output-names = "usb_l4_gate_ick";
0154 clocks = <&l4_ick>;
0155 ti,bit-shift = <5>;
0156 };
0157 };
0158
0159 ssi_l4_ick: ssi_l4_ick {
0160 #clock-cells = <0>;
0161 compatible = "fixed-factor-clock";
0162 clocks = <&l4_ick>;
0163 clock-mult = <1>;
0164 clock-div = <1>;
0165 };
0166
0167 usb_l4_ick: usb_l4_ick {
0168 #clock-cells = <0>;
0169 compatible = "ti,composite-clock";
0170 clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
0171 };
0172
0173 clock@e00 {
0174 compatible = "ti,clksel";
0175 reg = <0xe00>;
0176 #clock-cells = <2>;
0177 #address-cells = <0>;
0178
0179 dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 {
0180 #clock-cells = <0>;
0181 compatible = "ti,gate-clock";
0182 clock-output-names = "dss1_alwon_fck_3430es1";
0183 clocks = <&dpll4_m4x2_ck>;
0184 ti,bit-shift = <0>;
0185 ti,set-rate-parent;
0186 };
0187 };
0188
0189 dss_ick: dss_ick_3430es1@e10 {
0190 #clock-cells = <0>;
0191 compatible = "ti,omap3-no-wait-interface-clock";
0192 clocks = <&l4_ick>;
0193 reg = <0x0e10>;
0194 ti,bit-shift = <0>;
0195 };
0196 };
0197
0198 &cm_clockdomains {
0199 core_l3_clkdm: core_l3_clkdm {
0200 compatible = "ti,clockdomain";
0201 clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>;
0202 };
0203
0204 gfx_3430es1_clkdm: gfx_3430es1_clkdm {
0205 compatible = "ti,clockdomain";
0206 clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>;
0207 };
0208
0209 dss_clkdm: dss_clkdm {
0210 compatible = "ti,clockdomain";
0211 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
0212 <&dss1_alwon_fck>, <&dss_ick>;
0213 };
0214
0215 d2d_clkdm: d2d_clkdm {
0216 compatible = "ti,clockdomain";
0217 clocks = <&d2d_26m_fck>;
0218 };
0219
0220 core_l4_clkdm: core_l4_clkdm {
0221 compatible = "ti,clockdomain";
0222 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
0223 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
0224 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
0225 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
0226 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
0227 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
0228 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
0229 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
0230 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
0231 <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>;
0232 };
0233 };
