0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for OMAP3 SoC
0004 *
0005 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 #include <dt-bindings/bus/ti-sysc.h>
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/interrupt-controller/irq.h>
0011 #include <dt-bindings/pinctrl/omap.h>
0012
0013 / {
0014 compatible = "ti,omap3430", "ti,omap3";
0015 interrupt-parent = <&intc>;
0016 #address-cells = <1>;
0017 #size-cells = <1>;
0018 chosen { };
0019
0020 aliases {
0021 i2c0 = &i2c1;
0022 i2c1 = &i2c2;
0023 i2c2 = &i2c3;
0024 mmc0 = &mmc1;
0025 mmc1 = &mmc2;
0026 mmc2 = &mmc3;
0027 serial0 = &uart1;
0028 serial1 = &uart2;
0029 serial2 = &uart3;
0030 };
0031
0032 cpus {
0033 #address-cells = <1>;
0034 #size-cells = <0>;
0035
0036 cpu@0 {
0037 compatible = "arm,cortex-a8";
0038 device_type = "cpu";
0039 reg = <0x0>;
0040
0041 clocks = <&dpll1_ck>;
0042 clock-names = "cpu";
0043
0044 clock-latency = <300000>; /* From omap-cpufreq driver */
0045 };
0046 };
0047
0048 pmu@54000000 {
0049 compatible = "arm,cortex-a8-pmu";
0050 reg = <0x54000000 0x800000>;
0051 interrupts = <3>;
0052 ti,hwmods = "debugss";
0053 };
0054
0055 /*
0056 * The soc node represents the soc top level view. It is used for IPs
0057 * that are not memory mapped in the MPU view or for the MPU itself.
0058 */
0059 soc {
0060 compatible = "ti,omap-infra";
0061 mpu {
0062 compatible = "ti,omap3-mpu";
0063 ti,hwmods = "mpu";
0064 };
0065
0066 iva: iva {
0067 compatible = "ti,iva2.2";
0068 ti,hwmods = "iva";
0069
0070 dsp {
0071 compatible = "ti,omap3-c64";
0072 };
0073 };
0074 };
0075
0076 /*
0077 * XXX: Use a flat representation of the OMAP3 interconnect.
0078 * The real OMAP interconnect network is quite complex.
0079 * Since it will not bring real advantage to represent that in DT for
0080 * the moment, just use a fake OCP bus entry to represent the whole bus
0081 * hierarchy.
0082 */
0083 ocp@68000000 {
0084 compatible = "ti,omap3-l3-smx", "simple-bus";
0085 reg = <0x68000000 0x10000>;
0086 interrupts = <9 10>;
0087 #address-cells = <1>;
0088 #size-cells = <1>;
0089 ranges;
0090 ti,hwmods = "l3_main";
0091
0092 l4_core: l4@48000000 {
0093 compatible = "ti,omap3-l4-core", "simple-bus";
0094 #address-cells = <1>;
0095 #size-cells = <1>;
0096 ranges = <0 0x48000000 0x1000000>;
0097
0098 scm: scm@2000 {
0099 compatible = "ti,omap3-scm", "simple-bus";
0100 reg = <0x2000 0x2000>;
0101 #address-cells = <1>;
0102 #size-cells = <1>;
0103 ranges = <0 0x2000 0x2000>;
0104
0105 omap3_pmx_core: pinmux@30 {
0106 compatible = "ti,omap3-padconf",
0107 "pinctrl-single";
0108 reg = <0x30 0x238>;
0109 #address-cells = <1>;
0110 #size-cells = <0>;
0111 #pinctrl-cells = <1>;
0112 #interrupt-cells = <1>;
0113 interrupt-controller;
0114 pinctrl-single,register-width = <16>;
0115 pinctrl-single,function-mask = <0xff1f>;
0116 };
0117
0118 scm_conf: scm_conf@270 {
0119 compatible = "syscon", "simple-bus";
0120 reg = <0x270 0x330>;
0121 #address-cells = <1>;
0122 #size-cells = <1>;
0123 ranges = <0 0x270 0x330>;
0124
0125 pbias_regulator: pbias_regulator@2b0 {
0126 compatible = "ti,pbias-omap3", "ti,pbias-omap";
0127 reg = <0x2b0 0x4>;
0128 syscon = <&scm_conf>;
0129 pbias_mmc_reg: pbias_mmc_omap2430 {
0130 regulator-name = "pbias_mmc_omap2430";
0131 regulator-min-microvolt = <1800000>;
0132 regulator-max-microvolt = <3000000>;
0133 };
0134 };
0135
0136 scm_clocks: clocks {
0137 #address-cells = <1>;
0138 #size-cells = <0>;
0139 };
0140 };
0141
0142 scm_clockdomains: clockdomains {
0143 };
0144
0145 omap3_pmx_wkup: pinmux@a00 {
0146 compatible = "ti,omap3-padconf",
0147 "pinctrl-single";
0148 reg = <0xa00 0x5c>;
0149 #address-cells = <1>;
0150 #size-cells = <0>;
0151 #pinctrl-cells = <1>;
0152 #interrupt-cells = <1>;
0153 interrupt-controller;
0154 pinctrl-single,register-width = <16>;
0155 pinctrl-single,function-mask = <0xff1f>;
0156 };
0157 };
0158 };
0159
0160 aes1_target: target-module@480a6000 {
0161 compatible = "ti,sysc-omap2", "ti,sysc";
0162 reg = <0x480a6044 0x4>,
0163 <0x480a6048 0x4>,
0164 <0x480a604c 0x4>;
0165 reg-names = "rev", "sysc", "syss";
0166 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
0167 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0168 <SYSC_IDLE_NO>,
0169 <SYSC_IDLE_SMART>;
0170 ti,syss-mask = <1>;
0171 clocks = <&aes1_ick>;
0172 clock-names = "ick";
0173 #address-cells = <1>;
0174 #size-cells = <1>;
0175 ranges = <0 0x480a6000 0x2000>;
0176
0177 aes1: aes1@0 {
0178 compatible = "ti,omap3-aes";
0179 reg = <0 0x50>;
0180 interrupts = <0>;
0181 dmas = <&sdma 9 &sdma 10>;
0182 dma-names = "tx", "rx";
0183 };
0184 };
0185
0186 aes2_target: target-module@480c5000 {
0187 compatible = "ti,sysc-omap2", "ti,sysc";
0188 reg = <0x480c5044 0x4>,
0189 <0x480c5048 0x4>,
0190 <0x480c504c 0x4>;
0191 reg-names = "rev", "sysc", "syss";
0192 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
0193 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0194 <SYSC_IDLE_NO>,
0195 <SYSC_IDLE_SMART>;
0196 ti,syss-mask = <1>;
0197 clocks = <&aes2_ick>;
0198 clock-names = "ick";
0199 #address-cells = <1>;
0200 #size-cells = <1>;
0201 ranges = <0 0x480c5000 0x2000>;
0202
0203 aes2: aes2@0 {
0204 compatible = "ti,omap3-aes";
0205 reg = <0 0x50>;
0206 interrupts = <0>;
0207 dmas = <&sdma 65 &sdma 66>;
0208 dma-names = "tx", "rx";
0209 };
0210 };
0211
0212 prm: prm@48306000 {
0213 compatible = "ti,omap3-prm";
0214 reg = <0x48306000 0x4000>;
0215 interrupts = <11>;
0216
0217 prm_clocks: clocks {
0218 #address-cells = <1>;
0219 #size-cells = <0>;
0220 };
0221
0222 prm_clockdomains: clockdomains {
0223 };
0224 };
0225
0226 cm: cm@48004000 {
0227 compatible = "ti,omap3-cm";
0228 reg = <0x48004000 0x4000>;
0229
0230 cm_clocks: clocks {
0231 #address-cells = <1>;
0232 #size-cells = <0>;
0233 };
0234
0235 cm_clockdomains: clockdomains {
0236 };
0237 };
0238
0239 target-module@48320000 {
0240 compatible = "ti,sysc-omap2", "ti,sysc";
0241 reg = <0x48320000 0x4>,
0242 <0x48320004 0x4>;
0243 reg-names = "rev", "sysc";
0244 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0245 <SYSC_IDLE_NO>;
0246 clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>;
0247 clock-names = "fck", "ick";
0248 #address-cells = <1>;
0249 #size-cells = <1>;
0250 ranges = <0x0 0x48320000 0x1000>;
0251
0252 counter32k: counter@0 {
0253 compatible = "ti,omap-counter32k";
0254 reg = <0x0 0x20>;
0255 };
0256 };
0257
0258 intc: interrupt-controller@48200000 {
0259 compatible = "ti,omap3-intc";
0260 interrupt-controller;
0261 #interrupt-cells = <1>;
0262 reg = <0x48200000 0x1000>;
0263 };
0264
0265 target-module@48056000 {
0266 compatible = "ti,sysc-omap2", "ti,sysc";
0267 reg = <0x48056000 0x4>,
0268 <0x4805602c 0x4>,
0269 <0x48056028 0x4>;
0270 reg-names = "rev", "sysc", "syss";
0271 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0272 SYSC_OMAP2_EMUFREE |
0273 SYSC_OMAP2_SOFTRESET |
0274 SYSC_OMAP2_AUTOIDLE)>;
0275 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0276 <SYSC_IDLE_NO>,
0277 <SYSC_IDLE_SMART>;
0278 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0279 <SYSC_IDLE_NO>,
0280 <SYSC_IDLE_SMART>;
0281 ti,syss-mask = <1>;
0282 /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */
0283 clocks = <&core_l3_ick>;
0284 clock-names = "ick";
0285 #address-cells = <1>;
0286 #size-cells = <1>;
0287 ranges = <0 0x48056000 0x1000>;
0288
0289 sdma: dma-controller@0 {
0290 compatible = "ti,omap3430-sdma", "ti,omap-sdma";
0291 reg = <0x0 0x1000>;
0292 interrupts = <12>,
0293 <13>,
0294 <14>,
0295 <15>;
0296 #dma-cells = <1>;
0297 dma-channels = <32>;
0298 dma-requests = <96>;
0299 };
0300 };
0301
0302 gpio1: gpio@48310000 {
0303 compatible = "ti,omap3-gpio";
0304 reg = <0x48310000 0x200>;
0305 interrupts = <29>;
0306 ti,hwmods = "gpio1";
0307 ti,gpio-always-on;
0308 gpio-controller;
0309 #gpio-cells = <2>;
0310 interrupt-controller;
0311 #interrupt-cells = <2>;
0312 };
0313
0314 gpio2: gpio@49050000 {
0315 compatible = "ti,omap3-gpio";
0316 reg = <0x49050000 0x200>;
0317 interrupts = <30>;
0318 ti,hwmods = "gpio2";
0319 gpio-controller;
0320 #gpio-cells = <2>;
0321 interrupt-controller;
0322 #interrupt-cells = <2>;
0323 };
0324
0325 gpio3: gpio@49052000 {
0326 compatible = "ti,omap3-gpio";
0327 reg = <0x49052000 0x200>;
0328 interrupts = <31>;
0329 ti,hwmods = "gpio3";
0330 gpio-controller;
0331 #gpio-cells = <2>;
0332 interrupt-controller;
0333 #interrupt-cells = <2>;
0334 };
0335
0336 gpio4: gpio@49054000 {
0337 compatible = "ti,omap3-gpio";
0338 reg = <0x49054000 0x200>;
0339 interrupts = <32>;
0340 ti,hwmods = "gpio4";
0341 gpio-controller;
0342 #gpio-cells = <2>;
0343 interrupt-controller;
0344 #interrupt-cells = <2>;
0345 };
0346
0347 gpio5: gpio@49056000 {
0348 compatible = "ti,omap3-gpio";
0349 reg = <0x49056000 0x200>;
0350 interrupts = <33>;
0351 ti,hwmods = "gpio5";
0352 gpio-controller;
0353 #gpio-cells = <2>;
0354 interrupt-controller;
0355 #interrupt-cells = <2>;
0356 };
0357
0358 gpio6: gpio@49058000 {
0359 compatible = "ti,omap3-gpio";
0360 reg = <0x49058000 0x200>;
0361 interrupts = <34>;
0362 ti,hwmods = "gpio6";
0363 gpio-controller;
0364 #gpio-cells = <2>;
0365 interrupt-controller;
0366 #interrupt-cells = <2>;
0367 };
0368
0369 uart1: serial@4806a000 {
0370 compatible = "ti,omap3-uart";
0371 reg = <0x4806a000 0x2000>;
0372 interrupts-extended = <&intc 72>;
0373 dmas = <&sdma 49 &sdma 50>;
0374 dma-names = "tx", "rx";
0375 ti,hwmods = "uart1";
0376 clock-frequency = <48000000>;
0377 };
0378
0379 uart2: serial@4806c000 {
0380 compatible = "ti,omap3-uart";
0381 reg = <0x4806c000 0x400>;
0382 interrupts-extended = <&intc 73>;
0383 dmas = <&sdma 51 &sdma 52>;
0384 dma-names = "tx", "rx";
0385 ti,hwmods = "uart2";
0386 clock-frequency = <48000000>;
0387 };
0388
0389 uart3: serial@49020000 {
0390 compatible = "ti,omap3-uart";
0391 reg = <0x49020000 0x400>;
0392 interrupts-extended = <&intc 74>;
0393 dmas = <&sdma 53 &sdma 54>;
0394 dma-names = "tx", "rx";
0395 ti,hwmods = "uart3";
0396 clock-frequency = <48000000>;
0397 };
0398
0399 i2c1: i2c@48070000 {
0400 compatible = "ti,omap3-i2c";
0401 reg = <0x48070000 0x80>;
0402 interrupts = <56>;
0403 #address-cells = <1>;
0404 #size-cells = <0>;
0405 ti,hwmods = "i2c1";
0406 };
0407
0408 i2c2: i2c@48072000 {
0409 compatible = "ti,omap3-i2c";
0410 reg = <0x48072000 0x80>;
0411 interrupts = <57>;
0412 #address-cells = <1>;
0413 #size-cells = <0>;
0414 ti,hwmods = "i2c2";
0415 };
0416
0417 i2c3: i2c@48060000 {
0418 compatible = "ti,omap3-i2c";
0419 reg = <0x48060000 0x80>;
0420 interrupts = <61>;
0421 #address-cells = <1>;
0422 #size-cells = <0>;
0423 ti,hwmods = "i2c3";
0424 };
0425
0426 mailbox: mailbox@48094000 {
0427 compatible = "ti,omap3-mailbox";
0428 ti,hwmods = "mailbox";
0429 reg = <0x48094000 0x200>;
0430 interrupts = <26>;
0431 #mbox-cells = <1>;
0432 ti,mbox-num-users = <2>;
0433 ti,mbox-num-fifos = <2>;
0434 mbox_dsp: mbox-dsp {
0435 ti,mbox-tx = <0 0 0>;
0436 ti,mbox-rx = <1 0 0>;
0437 };
0438 };
0439
0440 mcspi1: spi@48098000 {
0441 compatible = "ti,omap2-mcspi";
0442 reg = <0x48098000 0x100>;
0443 interrupts = <65>;
0444 #address-cells = <1>;
0445 #size-cells = <0>;
0446 ti,hwmods = "mcspi1";
0447 ti,spi-num-cs = <4>;
0448 dmas = <&sdma 35>,
0449 <&sdma 36>,
0450 <&sdma 37>,
0451 <&sdma 38>,
0452 <&sdma 39>,
0453 <&sdma 40>,
0454 <&sdma 41>,
0455 <&sdma 42>;
0456 dma-names = "tx0", "rx0", "tx1", "rx1",
0457 "tx2", "rx2", "tx3", "rx3";
0458 };
0459
0460 mcspi2: spi@4809a000 {
0461 compatible = "ti,omap2-mcspi";
0462 reg = <0x4809a000 0x100>;
0463 interrupts = <66>;
0464 #address-cells = <1>;
0465 #size-cells = <0>;
0466 ti,hwmods = "mcspi2";
0467 ti,spi-num-cs = <2>;
0468 dmas = <&sdma 43>,
0469 <&sdma 44>,
0470 <&sdma 45>,
0471 <&sdma 46>;
0472 dma-names = "tx0", "rx0", "tx1", "rx1";
0473 };
0474
0475 mcspi3: spi@480b8000 {
0476 compatible = "ti,omap2-mcspi";
0477 reg = <0x480b8000 0x100>;
0478 interrupts = <91>;
0479 #address-cells = <1>;
0480 #size-cells = <0>;
0481 ti,hwmods = "mcspi3";
0482 ti,spi-num-cs = <2>;
0483 dmas = <&sdma 15>,
0484 <&sdma 16>,
0485 <&sdma 23>,
0486 <&sdma 24>;
0487 dma-names = "tx0", "rx0", "tx1", "rx1";
0488 };
0489
0490 mcspi4: spi@480ba000 {
0491 compatible = "ti,omap2-mcspi";
0492 reg = <0x480ba000 0x100>;
0493 interrupts = <48>;
0494 #address-cells = <1>;
0495 #size-cells = <0>;
0496 ti,hwmods = "mcspi4";
0497 ti,spi-num-cs = <1>;
0498 dmas = <&sdma 70>, <&sdma 71>;
0499 dma-names = "tx0", "rx0";
0500 };
0501
0502 hdqw1w: 1w@480b2000 {
0503 compatible = "ti,omap3-1w";
0504 reg = <0x480b2000 0x1000>;
0505 interrupts = <58>;
0506 ti,hwmods = "hdq1w";
0507 };
0508
0509 mmc1: mmc@4809c000 {
0510 compatible = "ti,omap3-hsmmc";
0511 reg = <0x4809c000 0x200>;
0512 interrupts = <83>;
0513 ti,hwmods = "mmc1";
0514 ti,dual-volt;
0515 dmas = <&sdma 61>, <&sdma 62>;
0516 dma-names = "tx", "rx";
0517 pbias-supply = <&pbias_mmc_reg>;
0518 };
0519
0520 mmc2: mmc@480b4000 {
0521 compatible = "ti,omap3-hsmmc";
0522 reg = <0x480b4000 0x200>;
0523 interrupts = <86>;
0524 ti,hwmods = "mmc2";
0525 dmas = <&sdma 47>, <&sdma 48>;
0526 dma-names = "tx", "rx";
0527 };
0528
0529 mmc3: mmc@480ad000 {
0530 compatible = "ti,omap3-hsmmc";
0531 reg = <0x480ad000 0x200>;
0532 interrupts = <94>;
0533 ti,hwmods = "mmc3";
0534 dmas = <&sdma 77>, <&sdma 78>;
0535 dma-names = "tx", "rx";
0536 };
0537
0538 mmu_isp: mmu@480bd400 {
0539 #iommu-cells = <0>;
0540 compatible = "ti,omap2-iommu";
0541 reg = <0x480bd400 0x80>;
0542 interrupts = <24>;
0543 ti,hwmods = "mmu_isp";
0544 ti,#tlb-entries = <8>;
0545 };
0546
0547 mmu_iva: mmu@5d000000 {
0548 #iommu-cells = <0>;
0549 compatible = "ti,omap2-iommu";
0550 reg = <0x5d000000 0x80>;
0551 interrupts = <28>;
0552 ti,hwmods = "mmu_iva";
0553 status = "disabled";
0554 };
0555
0556 wdt2: wdt@48314000 {
0557 compatible = "ti,omap3-wdt";
0558 reg = <0x48314000 0x80>;
0559 ti,hwmods = "wd_timer2";
0560 };
0561
0562 mcbsp1: mcbsp@48074000 {
0563 compatible = "ti,omap3-mcbsp";
0564 reg = <0x48074000 0xff>;
0565 reg-names = "mpu";
0566 interrupts = <16>, /* OCP compliant interrupt */
0567 <59>, /* TX interrupt */
0568 <60>; /* RX interrupt */
0569 interrupt-names = "common", "tx", "rx";
0570 ti,buffer-size = <128>;
0571 ti,hwmods = "mcbsp1";
0572 dmas = <&sdma 31>,
0573 <&sdma 32>;
0574 dma-names = "tx", "rx";
0575 clocks = <&mcbsp1_fck>;
0576 clock-names = "fck";
0577 status = "disabled";
0578 };
0579
0580 /* Likely needs to be tagged disabled on HS devices */
0581 rng_target: target-module@480a0000 {
0582 compatible = "ti,sysc-omap2", "ti,sysc";
0583 reg = <0x480a003c 0x4>,
0584 <0x480a0040 0x4>,
0585 <0x480a0044 0x4>;
0586 reg-names = "rev", "sysc", "syss";
0587 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
0588 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0589 <SYSC_IDLE_NO>;
0590 ti,syss-mask = <1>;
0591 clocks = <&rng_ick>;
0592 clock-names = "ick";
0593 #address-cells = <1>;
0594 #size-cells = <1>;
0595 ranges = <0 0x480a0000 0x2000>;
0596
0597 rng: rng@0 {
0598 compatible = "ti,omap2-rng";
0599 reg = <0x0 0x2000>;
0600 interrupts = <52>;
0601 };
0602 };
0603
0604 mcbsp2: mcbsp@49022000 {
0605 compatible = "ti,omap3-mcbsp";
0606 reg = <0x49022000 0xff>,
0607 <0x49028000 0xff>;
0608 reg-names = "mpu", "sidetone";
0609 interrupts = <17>, /* OCP compliant interrupt */
0610 <62>, /* TX interrupt */
0611 <63>, /* RX interrupt */
0612 <4>; /* Sidetone */
0613 interrupt-names = "common", "tx", "rx", "sidetone";
0614 ti,buffer-size = <1280>;
0615 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
0616 dmas = <&sdma 33>,
0617 <&sdma 34>;
0618 dma-names = "tx", "rx";
0619 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
0620 clock-names = "fck", "ick";
0621 status = "disabled";
0622 };
0623
0624 mcbsp3: mcbsp@49024000 {
0625 compatible = "ti,omap3-mcbsp";
0626 reg = <0x49024000 0xff>,
0627 <0x4902a000 0xff>;
0628 reg-names = "mpu", "sidetone";
0629 interrupts = <22>, /* OCP compliant interrupt */
0630 <89>, /* TX interrupt */
0631 <90>, /* RX interrupt */
0632 <5>; /* Sidetone */
0633 interrupt-names = "common", "tx", "rx", "sidetone";
0634 ti,buffer-size = <128>;
0635 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
0636 dmas = <&sdma 17>,
0637 <&sdma 18>;
0638 dma-names = "tx", "rx";
0639 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
0640 clock-names = "fck", "ick";
0641 status = "disabled";
0642 };
0643
0644 mcbsp4: mcbsp@49026000 {
0645 compatible = "ti,omap3-mcbsp";
0646 reg = <0x49026000 0xff>;
0647 reg-names = "mpu";
0648 interrupts = <23>, /* OCP compliant interrupt */
0649 <54>, /* TX interrupt */
0650 <55>; /* RX interrupt */
0651 interrupt-names = "common", "tx", "rx";
0652 ti,buffer-size = <128>;
0653 ti,hwmods = "mcbsp4";
0654 dmas = <&sdma 19>,
0655 <&sdma 20>;
0656 dma-names = "tx", "rx";
0657 clocks = <&mcbsp4_fck>;
0658 clock-names = "fck";
0659 #sound-dai-cells = <0>;
0660 status = "disabled";
0661 };
0662
0663 mcbsp5: mcbsp@48096000 {
0664 compatible = "ti,omap3-mcbsp";
0665 reg = <0x48096000 0xff>;
0666 reg-names = "mpu";
0667 interrupts = <27>, /* OCP compliant interrupt */
0668 <81>, /* TX interrupt */
0669 <82>; /* RX interrupt */
0670 interrupt-names = "common", "tx", "rx";
0671 ti,buffer-size = <128>;
0672 ti,hwmods = "mcbsp5";
0673 dmas = <&sdma 21>,
0674 <&sdma 22>;
0675 dma-names = "tx", "rx";
0676 clocks = <&mcbsp5_fck>;
0677 clock-names = "fck";
0678 status = "disabled";
0679 };
0680
0681 sham: sham@480c3000 {
0682 compatible = "ti,omap3-sham";
0683 ti,hwmods = "sham";
0684 reg = <0x480c3000 0x64>;
0685 interrupts = <49>;
0686 dmas = <&sdma 69>;
0687 dma-names = "rx";
0688 };
0689
0690 timer1_target: target-module@48318000 {
0691 compatible = "ti,sysc-omap2-timer", "ti,sysc";
0692 reg = <0x48318000 0x4>,
0693 <0x48318010 0x4>,
0694 <0x48318014 0x4>;
0695 reg-names = "rev", "sysc", "syss";
0696 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0697 SYSC_OMAP2_EMUFREE |
0698 SYSC_OMAP2_ENAWAKEUP |
0699 SYSC_OMAP2_SOFTRESET |
0700 SYSC_OMAP2_AUTOIDLE)>;
0701 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0702 <SYSC_IDLE_NO>,
0703 <SYSC_IDLE_SMART>;
0704 ti,syss-mask = <1>;
0705 clocks = <&gpt1_fck>, <&gpt1_ick>;
0706 clock-names = "fck", "ick";
0707 #address-cells = <1>;
0708 #size-cells = <1>;
0709 ranges = <0x0 0x48318000 0x1000>;
0710
0711 timer1: timer@0 {
0712 compatible = "ti,omap3430-timer";
0713 reg = <0x0 0x80>;
0714 clocks = <&gpt1_fck>;
0715 clock-names = "fck";
0716 interrupts = <37>;
0717 ti,timer-alwon;
0718 };
0719 };
0720
0721 timer2_target: target-module@49032000 {
0722 compatible = "ti,sysc-omap2-timer", "ti,sysc";
0723 reg = <0x49032000 0x4>,
0724 <0x49032010 0x4>,
0725 <0x49032014 0x4>;
0726 reg-names = "rev", "sysc", "syss";
0727 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0728 SYSC_OMAP2_EMUFREE |
0729 SYSC_OMAP2_ENAWAKEUP |
0730 SYSC_OMAP2_SOFTRESET |
0731 SYSC_OMAP2_AUTOIDLE)>;
0732 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0733 <SYSC_IDLE_NO>,
0734 <SYSC_IDLE_SMART>;
0735 ti,syss-mask = <1>;
0736 clocks = <&gpt2_fck>, <&gpt2_ick>;
0737 clock-names = "fck", "ick";
0738 #address-cells = <1>;
0739 #size-cells = <1>;
0740 ranges = <0x0 0x49032000 0x1000>;
0741
0742 timer2: timer@0 {
0743 compatible = "ti,omap3430-timer";
0744 reg = <0 0x400>;
0745 interrupts = <38>;
0746 };
0747 };
0748
0749 timer3: timer@49034000 {
0750 compatible = "ti,omap3430-timer";
0751 reg = <0x49034000 0x400>;
0752 interrupts = <39>;
0753 ti,hwmods = "timer3";
0754 };
0755
0756 timer4: timer@49036000 {
0757 compatible = "ti,omap3430-timer";
0758 reg = <0x49036000 0x400>;
0759 interrupts = <40>;
0760 ti,hwmods = "timer4";
0761 };
0762
0763 timer5: timer@49038000 {
0764 compatible = "ti,omap3430-timer";
0765 reg = <0x49038000 0x400>;
0766 interrupts = <41>;
0767 ti,hwmods = "timer5";
0768 ti,timer-dsp;
0769 };
0770
0771 timer6: timer@4903a000 {
0772 compatible = "ti,omap3430-timer";
0773 reg = <0x4903a000 0x400>;
0774 interrupts = <42>;
0775 ti,hwmods = "timer6";
0776 ti,timer-dsp;
0777 };
0778
0779 timer7: timer@4903c000 {
0780 compatible = "ti,omap3430-timer";
0781 reg = <0x4903c000 0x400>;
0782 interrupts = <43>;
0783 ti,hwmods = "timer7";
0784 ti,timer-dsp;
0785 };
0786
0787 timer8: timer@4903e000 {
0788 compatible = "ti,omap3430-timer";
0789 reg = <0x4903e000 0x400>;
0790 interrupts = <44>;
0791 ti,hwmods = "timer8";
0792 ti,timer-pwm;
0793 ti,timer-dsp;
0794 };
0795
0796 timer9: timer@49040000 {
0797 compatible = "ti,omap3430-timer";
0798 reg = <0x49040000 0x400>;
0799 interrupts = <45>;
0800 ti,hwmods = "timer9";
0801 ti,timer-pwm;
0802 };
0803
0804 timer10: timer@48086000 {
0805 compatible = "ti,omap3430-timer";
0806 reg = <0x48086000 0x400>;
0807 interrupts = <46>;
0808 ti,hwmods = "timer10";
0809 ti,timer-pwm;
0810 };
0811
0812 timer11: timer@48088000 {
0813 compatible = "ti,omap3430-timer";
0814 reg = <0x48088000 0x400>;
0815 interrupts = <47>;
0816 ti,hwmods = "timer11";
0817 ti,timer-pwm;
0818 };
0819
0820 timer12_target: target-module@48304000 {
0821 compatible = "ti,sysc-omap2-timer", "ti,sysc";
0822 reg = <0x48304000 0x4>,
0823 <0x48304010 0x4>,
0824 <0x48304014 0x4>;
0825 reg-names = "rev", "sysc", "syss";
0826 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0827 SYSC_OMAP2_EMUFREE |
0828 SYSC_OMAP2_ENAWAKEUP |
0829 SYSC_OMAP2_SOFTRESET |
0830 SYSC_OMAP2_AUTOIDLE)>;
0831 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0832 <SYSC_IDLE_NO>,
0833 <SYSC_IDLE_SMART>;
0834 ti,syss-mask = <1>;
0835 clocks = <&gpt12_fck>, <&gpt12_ick>;
0836 clock-names = "fck", "ick";
0837 #address-cells = <1>;
0838 #size-cells = <1>;
0839 ranges = <0x0 0x48304000 0x1000>;
0840
0841 timer12: timer@0 {
0842 compatible = "ti,omap3430-timer";
0843 reg = <0 0x400>;
0844 interrupts = <95>;
0845 ti,timer-alwon;
0846 ti,timer-secure;
0847 };
0848 };
0849
0850 usbhstll: usbhstll@48062000 {
0851 compatible = "ti,usbhs-tll";
0852 reg = <0x48062000 0x1000>;
0853 interrupts = <78>;
0854 ti,hwmods = "usb_tll_hs";
0855 };
0856
0857 usbhshost: usbhshost@48064000 {
0858 compatible = "ti,usbhs-host";
0859 reg = <0x48064000 0x400>;
0860 ti,hwmods = "usb_host_hs";
0861 #address-cells = <1>;
0862 #size-cells = <1>;
0863 ranges;
0864
0865 usbhsohci: ohci@48064400 {
0866 compatible = "ti,ohci-omap3";
0867 reg = <0x48064400 0x400>;
0868 interrupts = <76>;
0869 remote-wakeup-connected;
0870 };
0871
0872 usbhsehci: ehci@48064800 {
0873 compatible = "ti,ehci-omap";
0874 reg = <0x48064800 0x400>;
0875 interrupts = <77>;
0876 };
0877 };
0878
0879 gpmc: gpmc@6e000000 {
0880 compatible = "ti,omap3430-gpmc";
0881 ti,hwmods = "gpmc";
0882 reg = <0x6e000000 0x02d0>;
0883 interrupts = <20>;
0884 dmas = <&sdma 4>;
0885 dma-names = "rxtx";
0886 gpmc,num-cs = <8>;
0887 gpmc,num-waitpins = <4>;
0888 #address-cells = <2>;
0889 #size-cells = <1>;
0890 interrupt-controller;
0891 #interrupt-cells = <2>;
0892 gpio-controller;
0893 #gpio-cells = <2>;
0894 };
0895
0896 usb_otg_hs: usb_otg_hs@480ab000 {
0897 compatible = "ti,omap3-musb";
0898 reg = <0x480ab000 0x1000>;
0899 interrupts = <92>, <93>;
0900 interrupt-names = "mc", "dma";
0901 ti,hwmods = "usb_otg_hs";
0902 multipoint = <1>;
0903 num-eps = <16>;
0904 ram-bits = <12>;
0905 };
0906
0907 dss: dss@48050000 {
0908 compatible = "ti,omap3-dss";
0909 reg = <0x48050000 0x200>;
0910 status = "disabled";
0911 ti,hwmods = "dss_core";
0912 clocks = <&dss1_alwon_fck>;
0913 clock-names = "fck";
0914 #address-cells = <1>;
0915 #size-cells = <1>;
0916 ranges;
0917
0918 dispc@48050400 {
0919 compatible = "ti,omap3-dispc";
0920 reg = <0x48050400 0x400>;
0921 interrupts = <25>;
0922 ti,hwmods = "dss_dispc";
0923 clocks = <&dss1_alwon_fck>;
0924 clock-names = "fck";
0925 };
0926
0927 dsi: encoder@4804fc00 {
0928 compatible = "ti,omap3-dsi";
0929 reg = <0x4804fc00 0x200>,
0930 <0x4804fe00 0x40>,
0931 <0x4804ff00 0x20>;
0932 reg-names = "proto", "phy", "pll";
0933 interrupts = <25>;
0934 status = "disabled";
0935 ti,hwmods = "dss_dsi1";
0936 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
0937 clock-names = "fck", "sys_clk";
0938
0939 #address-cells = <1>;
0940 #size-cells = <0>;
0941 };
0942
0943 rfbi: encoder@48050800 {
0944 compatible = "ti,omap3-rfbi";
0945 reg = <0x48050800 0x100>;
0946 status = "disabled";
0947 ti,hwmods = "dss_rfbi";
0948 clocks = <&dss1_alwon_fck>, <&dss_ick>;
0949 clock-names = "fck", "ick";
0950 };
0951
0952 venc: encoder@48050c00 {
0953 compatible = "ti,omap3-venc";
0954 reg = <0x48050c00 0x100>;
0955 status = "disabled";
0956 ti,hwmods = "dss_venc";
0957 clocks = <&dss_tv_fck>;
0958 clock-names = "fck";
0959 };
0960 };
0961
0962 ssi: ssi-controller@48058000 {
0963 compatible = "ti,omap3-ssi";
0964 ti,hwmods = "ssi";
0965
0966 status = "disabled";
0967
0968 reg = <0x48058000 0x1000>,
0969 <0x48059000 0x1000>;
0970 reg-names = "sys",
0971 "gdd";
0972
0973 interrupts = <71>;
0974 interrupt-names = "gdd_mpu";
0975
0976 #address-cells = <1>;
0977 #size-cells = <1>;
0978 ranges;
0979
0980 ssi_port1: ssi-port@4805a000 {
0981 compatible = "ti,omap3-ssi-port";
0982
0983 reg = <0x4805a000 0x800>,
0984 <0x4805a800 0x800>;
0985 reg-names = "tx",
0986 "rx";
0987
0988 interrupts = <67>,
0989 <68>;
0990 };
0991
0992 ssi_port2: ssi-port@4805b000 {
0993 compatible = "ti,omap3-ssi-port";
0994
0995 reg = <0x4805b000 0x800>,
0996 <0x4805b800 0x800>;
0997 reg-names = "tx",
0998 "rx";
0999
1000 interrupts = <69>,
1001 <70>;
1002 };
1003 };
1004 };
1005 };
1006
1007 #include "omap3xxx-clocks.dtsi"
1008
1009 /* Preferred always-on timer for clockevent. Some boards must use dmtimer12 */
1010 &timer1_target {
1011 ti,no-reset-on-init;
1012 ti,no-idle;
1013 timer@0 {
1014 assigned-clocks = <&gpt1_fck>;
1015 assigned-clock-parents = <&omap_32k_fck>;
1016 };
1017 };
