0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
0004 */
0005
0006 /*
0007 * The Gumstix Overo must be combined with an expansion board.
0008 */
0009
0010 / {
0011
0012 memory@0 {
0013 device_type = "memory";
0014 reg = <0 0>;
0015 };
0016
0017 led-controller {
0018 compatible = "pwm-leds";
0019
0020 led-1 {
0021 label = "overo:blue:COM";
0022 pwms = <&twl_pwmled 1 7812500>;
0023 max-brightness = <127>;
0024 linux,default-trigger = "mmc0";
0025 };
0026 };
0027
0028 sound {
0029 compatible = "ti,omap-twl4030";
0030 ti,model = "overo";
0031
0032 ti,mcbsp = <&mcbsp2>;
0033 };
0034
0035 /* HS USB Port 2 Power */
0036 hsusb2_power: hsusb2_power_reg {
0037 compatible = "regulator-fixed";
0038 regulator-name = "hsusb2_vbus";
0039 regulator-min-microvolt = <5000000>;
0040 regulator-max-microvolt = <5000000>;
0041 gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>; /* gpio_168: vbus enable */
0042 startup-delay-us = <70000>;
0043 enable-active-high;
0044 };
0045
0046 /* HS USB Host PHY on PORT 2 */
0047 hsusb2_phy: hsusb2_phy {
0048 compatible = "usb-nop-xceiv";
0049 reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; /* gpio_183 */
0050 vcc-supply = <&hsusb2_power>;
0051 #phy-cells = <0>;
0052 };
0053
0054 /* Regulator to trigger the nPoweron signal of the Wifi module */
0055 w3cbw003c_npoweron: regulator-w3cbw003c-npoweron {
0056 compatible = "regulator-fixed";
0057 regulator-name = "regulator-w3cbw003c-npoweron";
0058 regulator-min-microvolt = <3300000>;
0059 regulator-max-microvolt = <3300000>;
0060 gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54: nPoweron */
0061 enable-active-high;
0062 };
0063
0064 /* Regulator to trigger the nReset signal of the Wifi module */
0065 w3cbw003c_wifi_nreset: regulator-w3cbw003c-wifi-nreset {
0066 pinctrl-names = "default";
0067 pinctrl-0 = <&w3cbw003c_pins &w3cbw003c_2_pins>;
0068 compatible = "regulator-fixed";
0069 regulator-name = "regulator-w3cbw003c-wifi-nreset";
0070 regulator-min-microvolt = <3300000>;
0071 regulator-max-microvolt = <3300000>;
0072 gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* gpio_16: WiFi nReset */
0073 startup-delay-us = <10000>;
0074 };
0075 };
0076
0077 &omap3_pmx_core {
0078 pinctrl-names = "default";
0079 pinctrl-0 = <
0080 &hsusb2_pins
0081 >;
0082
0083 uart2_pins: pinmux_uart2_pins {
0084 pinctrl-single,pins = <
0085 OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */
0086 OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */
0087 OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */
0088 OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */
0089 >;
0090 };
0091
0092 i2c1_pins: pinmux_i2c1_pins {
0093 pinctrl-single,pins = <
0094 OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
0095 OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
0096 >;
0097 };
0098
0099 mmc1_pins: pinmux_mmc1_pins {
0100 pinctrl-single,pins = <
0101 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
0102 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
0103 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
0104 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
0105 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
0106 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
0107 >;
0108 };
0109
0110 mmc2_pins: pinmux_mmc2_pins {
0111 pinctrl-single,pins = <
0112 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
0113 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
0114 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
0115 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
0116 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
0117 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
0118 >;
0119 };
0120
0121 /* WiFi/BT combo */
0122 w3cbw003c_pins: pinmux_w3cbw003c_pins {
0123 pinctrl-single,pins = <
0124 OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
0125 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */
0126 >;
0127 };
0128
0129 hsusb2_pins: pinmux_hsusb2_pins {
0130 pinctrl-single,pins = <
0131 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
0132 OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
0133 OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
0134 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
0135 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
0136 OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
0137 OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */
0138 OMAP3_CORE1_IOPAD(0x21c0, PIN_OUTPUT | MUX_MODE4) /* i2c2_sda.gpio_183 */
0139 >;
0140 };
0141 };
0142
0143 &i2c1 {
0144 pinctrl-names = "default";
0145 pinctrl-0 = <&i2c1_pins>;
0146 clock-frequency = <2600000>;
0147
0148 twl: twl@48 {
0149 reg = <0x48>;
0150 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
0151 interrupt-parent = <&intc>;
0152
0153 twl_audio: audio {
0154 compatible = "ti,twl4030-audio";
0155 codec {
0156 };
0157 };
0158 };
0159 };
0160
0161 #include "twl4030.dtsi"
0162 #include "twl4030_omap3.dtsi"
0163
0164 /* i2c2 pins are used for gpio */
0165 &i2c2 {
0166 status = "disabled";
0167 };
0168
0169 /* on board microSD slot */
0170 &mmc1 {
0171 pinctrl-names = "default";
0172 pinctrl-0 = <&mmc1_pins>;
0173 vmmc-supply = <&vmmc1>;
0174 bus-width = <4>;
0175 };
0176
0177 /* optional on board WiFi */
0178 &mmc2 {
0179 pinctrl-names = "default";
0180 pinctrl-0 = <&mmc2_pins>;
0181 vmmc-supply = <&w3cbw003c_npoweron>;
0182 vqmmc-supply = <&w3cbw003c_wifi_nreset>;
0183 bus-width = <4>;
0184 cap-sdio-irq;
0185 non-removable;
0186 };
0187
0188 &twl_gpio {
0189 ti,use-leds;
0190 };
0191
0192 &usb_otg_hs {
0193 interface-type = <0>;
0194 usb-phy = <&usb2_phy>;
0195 phys = <&usb2_phy>;
0196 phy-names = "usb2-phy";
0197 mode = <3>;
0198 power = <50>;
0199 };
0200
0201 &usbhshost {
0202 port2-mode = "ehci-phy";
0203 };
0204
0205 &usbhsehci {
0206 phys = <0 &hsusb2_phy>;
0207 };
0208
0209 &uart2 {
0210 pinctrl-names = "default";
0211 pinctrl-0 = <&uart2_pins>;
0212 };
0213
0214 &mcbsp2 {
0215 status = "okay";
0216 };
0217
0218 &gpmc {
0219 ranges = <0 0 0x30000000 0x1000000>, /* CS0 */
0220 <4 0 0x2b000000 0x1000000>, /* CS4 */
0221 <5 0 0x2c000000 0x1000000>; /* CS5 */
0222
0223 nand@0,0 {
0224 compatible = "ti,omap2-nand";
0225 linux,mtd-name = "micron,mt29c4g96maz";
0226 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
0227 interrupt-parent = <&gpmc>;
0228 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
0229 <1 IRQ_TYPE_NONE>; /* termcount */
0230 nand-bus-width = <16>;
0231 gpmc,device-width = <2>;
0232 ti,nand-ecc-opt = "bch8";
0233
0234 gpmc,sync-clk-ps = <0>;
0235 gpmc,cs-on-ns = <0>;
0236 gpmc,cs-rd-off-ns = <44>;
0237 gpmc,cs-wr-off-ns = <44>;
0238 gpmc,adv-on-ns = <6>;
0239 gpmc,adv-rd-off-ns = <34>;
0240 gpmc,adv-wr-off-ns = <44>;
0241 gpmc,we-off-ns = <40>;
0242 gpmc,oe-off-ns = <54>;
0243 gpmc,access-ns = <64>;
0244 gpmc,rd-cycle-ns = <82>;
0245 gpmc,wr-cycle-ns = <82>;
0246 gpmc,wr-access-ns = <40>;
0247 gpmc,wr-data-mux-bus-ns = <0>;
0248
0249 #address-cells = <1>;
0250 #size-cells = <1>;
0251
0252 partition@0 {
0253 label = "SPL";
0254 reg = <0 0x80000>; /* 512KiB */
0255 };
0256 partition@80000 {
0257 label = "U-Boot";
0258 reg = <0x80000 0x1C0000>; /* 1792KiB */
0259 };
0260 partition@1c0000 {
0261 label = "Environment";
0262 reg = <0x240000 0x40000>; /* 256KiB */
0263 };
0264 partition@280000 {
0265 label = "Kernel";
0266 reg = <0x280000 0x800000>; /* 8192KiB */
0267 };
0268 partition@780000 {
0269 label = "Filesystem";
0270 reg = <0xA80000 0>;
0271 /* HACK: MTDPART_SIZ_FULL=0 so fill to end */
0272 };
0273 };
0274 };
