0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Copyright (C) 2014 Christoph Fritz <chf.fritzc@googlemail.com>
0004 */
0005 /dts-v1/;
0006
0007 #include "omap3-lilly-a83x.dtsi"
0008
0009 / {
0010 model = "INCOstartec LILLY-DBB056 (DM3730)";
0011 compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap36xx", "ti,omap3";
0012 };
0013
0014 &twl {
0015 vaux2: regulator-vaux2 {
0016 compatible = "ti,twl4030-vaux2";
0017 regulator-min-microvolt = <2800000>;
0018 regulator-max-microvolt = <2800000>;
0019 regulator-always-on;
0020 };
0021 };
0022
0023 &omap3_pmx_core {
0024 pinctrl-names = "default";
0025 pinctrl-0 = <&lcd_pins>;
0026
0027 lan9117_pins: pinmux_lan9117_pins {
0028 pinctrl-single,pins = <
0029 OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* cam_fld.gpio_98 */
0030 >;
0031 };
0032
0033 gpio4_pins: pinmux_gpio4_pins {
0034 pinctrl-single,pins = <
0035 OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* cam_xclkb.gpio_111 -> sja1000 IRQ */
0036 >;
0037 };
0038
0039 gpio5_pins: pinmux_gpio5_pins {
0040 pinctrl-single,pins = <
0041 OMAP3_CORE1_IOPAD(0x218c, PIN_OUTPUT | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcbsp1_clk.gpio_156 -> enable DSS */
0042 >;
0043 };
0044
0045 lcd_pins: pinmux_lcd_pins {
0046 pinctrl-single,pins = <
0047 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
0048 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
0049 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
0050 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
0051 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
0052 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
0053 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
0054 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
0055 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
0056 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
0057 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
0058 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
0059 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
0060 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
0061 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
0062 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
0063 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
0064 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
0065 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
0066 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
0067 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
0068 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
0069 >;
0070 };
0071
0072 mmc2_pins: pinmux_mmc2_pins {
0073 pinctrl-single,pins = <
0074 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
0075 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
0076 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
0077 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
0078 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
0079 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
0080 OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */
0081 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */
0082 OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */
0083 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */
0084 OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 -> wp */
0085 OMAP3_CORE1_IOPAD(0x219c, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_rts_sd.gpio_164 -> cd */
0086 >;
0087 };
0088
0089 spi1_pins: pinmux_spi1_pins {
0090 pinctrl-single,pins = <
0091 OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
0092 OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
0093 OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
0094 OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
0095 >;
0096 };
0097 };
0098
0099 &gpio4 {
0100 pinctrl-names = "default";
0101 pinctrl-0 = <&gpio4_pins>;
0102 };
0103
0104 &gpio5 {
0105 pinctrl-names = "default";
0106 pinctrl-0 = <&gpio5_pins>;
0107 };
0108
0109 &mmc2 {
0110 status = "okay";
0111 bus-width = <4>;
0112 vmmc-supply = <&vmmc1>;
0113 cd-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio_164 */
0114 wp-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* gpio_163 */
0115 pinctrl-names = "default";
0116 pinctrl-0 = <&mmc2_pins>;
0117 ti,dual-volt;
0118 };
0119
0120 &mcspi1 {
0121 status = "okay";
0122 pinctrl-names = "default";
0123 pinctrl-0 = <&spi1_pins>;
0124 };
0125
0126 &gpmc {
0127 ranges = <0 0 0x30000000 0x1000000>, /* nand assigned by COM a83x */
0128 <4 0 0x20000000 0x01000000>,
0129 <7 0 0x15000000 0x01000000>; /* eth assigend by COM a83x */
0130
0131 ethernet@4,0 {
0132 compatible = "smsc,lan9117", "smsc,lan9115";
0133 bank-width = <2>;
0134 gpmc,mux-add-data = <2>;
0135 gpmc,cs-on-ns = <10>;
0136 gpmc,cs-rd-off-ns = <65>;
0137 gpmc,cs-wr-off-ns = <65>;
0138 gpmc,adv-on-ns = <0>;
0139 gpmc,adv-rd-off-ns = <10>;
0140 gpmc,adv-wr-off-ns = <10>;
0141 gpmc,oe-on-ns = <10>;
0142 gpmc,oe-off-ns = <65>;
0143 gpmc,we-on-ns = <10>;
0144 gpmc,we-off-ns = <65>;
0145 gpmc,rd-cycle-ns = <100>;
0146 gpmc,wr-cycle-ns = <100>;
0147 gpmc,access-ns = <60>;
0148 gpmc,page-burst-access-ns = <5>;
0149 gpmc,bus-turnaround-ns = <0>;
0150 gpmc,cycle2cycle-delay-ns = <75>;
0151 gpmc,wr-data-mux-bus-ns = <15>;
0152 gpmc,wr-access-ns = <75>;
0153 gpmc,cycle2cycle-samecsen;
0154 gpmc,cycle2cycle-diffcsen;
0155 vddvario-supply = <®_vcc3>;
0156 vdd33a-supply = <®_vcc3>;
0157 reg-io-width = <4>;
0158 interrupt-parent = <&gpio4>;
0159 interrupts = <2 0x2>;
0160 reg = <4 0 0xff>;
0161 pinctrl-names = "default";
0162 pinctrl-0 = <&lan9117_pins>;
0163 phy-mode = "mii";
0164 smsc,force-internal-phy;
0165 };
0166 };
