0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Common Device Tree Source for IGEP COM MODULE
0004 *
0005 * Copyright (C) 2014 Javier Martinez Canillas <javier@dowhile0.org>
0006 * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
0007 */
0008
0009 #include "omap3-igep.dtsi"
0010
0011 / {
0012 leds: gpio_leds {
0013 compatible = "gpio-leds";
0014
0015 user0 {
0016 label = "omap3:red:user0";
0017 gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
0018 default-state = "off";
0019 };
0020
0021 user1 {
0022 label = "omap3:green:user1";
0023 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
0024 default-state = "off";
0025 };
0026
0027 user2 {
0028 label = "omap3:red:user1";
0029 gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* gpio_16 */
0030 default-state = "off";
0031 };
0032 };
0033
0034 hsusb2_phy: hsusb2_phy {
0035 compatible = "usb-nop-xceiv";
0036 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */
0037 #phy-cells = <0>;
0038 };
0039 };
0040
0041 &omap3_pmx_core {
0042 pinctrl-names = "default";
0043 pinctrl-0 = <&hsusb2_pins>;
0044
0045 hsusb2_pins: pinmux_hsusb2_pins {
0046 pinctrl-single,pins = <
0047 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
0048 OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
0049 OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
0050 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
0051 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
0052 OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
0053 >;
0054 };
0055
0056 uart2_pins: pinmux_uart2_pins {
0057 pinctrl-single,pins = <
0058 OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */
0059 OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */
0060 OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */
0061 OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */
0062 >;
0063 };
0064 };
0065
0066 &omap3_pmx_core2 {
0067 pinctrl-names = "default";
0068 pinctrl-0 = <&hsusb2_core2_pins>;
0069
0070 hsusb2_core2_pins: pinmux_hsusb2_core2_pins {
0071 pinctrl-single,pins = <
0072 OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
0073 OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
0074 OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
0075 OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
0076 OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
0077 OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
0078 >;
0079 };
0080
0081 leds_core2_pins: pinmux_leds_core2_pins {
0082 pinctrl-single,pins = <
0083 OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
0084 >;
0085 };
0086 };
0087
0088 &usbhshost {
0089 port2-mode = "ehci-phy";
0090 };
0091
0092 &usbhsehci {
0093 phys = <0 &hsusb2_phy>;
0094 };
0095
0096 &uart2 {
0097 pinctrl-names = "default";
0098 pinctrl-0 = <&uart2_pins>;
0099 };
0100
0101 &gpmc {
0102 ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */
0103 };
