0001 /*
0002 * Common support for omap3 EVM 35xx/37xx processor modules
0003 */
0004
0005 / {
0006 memory@80000000 {
0007 device_type = "memory";
0008 reg = <0x80000000 0x10000000>; /* 256 MB */
0009 };
0010
0011 wl12xx_vmmc: wl12xx_vmmc {
0012 pinctrl-names = "default";
0013 pinctrl-0 = <&wl12xx_gpio>;
0014 };
0015 };
0016
0017 &dss {
0018 vdds_dsi-supply = <&vpll2>;
0019 vdda_video-supply = <&lcd_3v3>;
0020 pinctrl-names = "default";
0021 pinctrl-0 = <
0022 &dss_dpi_pins1
0023 &dss_dpi_pins2
0024 >;
0025 };
0026
0027 &hsusb2_phy {
0028 pinctrl-names = "default";
0029 pinctrl-0 = <&ehci_phy_pins>;
0030 };
0031
0032 &omap3_pmx_core {
0033 pinctrl-names = "default";
0034 pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>;
0035
0036 dss_dpi_pins1: pinmux_dss_dpi_pins2 {
0037 pinctrl-single,pins = <
0038 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
0039 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
0040 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
0041 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
0042
0043 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
0044 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
0045 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
0046 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
0047 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
0048 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
0049 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
0050 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
0051 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
0052 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
0053 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
0054 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
0055
0056 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */
0057 OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */
0058 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */
0059 OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */
0060 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */
0061 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */
0062 >;
0063 };
0064
0065 mmc1_pins: pinmux_mmc1_pins {
0066 pinctrl-single,pins = <
0067 OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
0068 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
0069 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
0070 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
0071 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
0072 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
0073 OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */
0074 OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */
0075 OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */
0076 OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */
0077 >;
0078 };
0079
0080 /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */
0081 mmc2_pins: pinmux_mmc2_pins {
0082 pinctrl-single,pins = <
0083 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
0084 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
0085 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
0086 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
0087 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
0088 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
0089 OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */
0090 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */
0091 OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */
0092 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */
0093 >;
0094 };
0095
0096 uart3_pins: pinmux_uart3_pins {
0097 pinctrl-single,pins = <
0098 OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
0099 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
0100 >;
0101 };
0102
0103 /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */
0104 on_board_gpio_61: pinmux_ehci_port_select_pins {
0105 pinctrl-single,pins = <
0106 OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4)
0107 >;
0108 };
0109
0110 /* Used by OHCI and EHCI. OHCI won't work without external phy */
0111 hsusb2_pins: pinmux_hsusb2_pins {
0112 pinctrl-single,pins = <
0113
0114 /* mcspi1_cs3.hsusb2_data2 */
0115 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)
0116
0117 /* mcspi2_clk.hsusb2_data7 */
0118 OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)
0119
0120 /* mcspi2_simo.hsusb2_data4 */
0121 OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)
0122
0123 /* mcspi2_somi.hsusb2_data5 */
0124 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)
0125
0126 /* mcspi2_cs0.hsusb2_data6 */
0127 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)
0128
0129 /* mcspi2_cs1.hsusb2_data3 */
0130 OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)
0131 >;
0132 };
0133
0134 /*
0135 * Note that gpio_150 pulled high with internal pull to prevent wlcore
0136 * reset on return from off mode in idle.
0137 */
0138 wl12xx_gpio: pinmux_wl12xx_gpio {
0139 pinctrl-single,pins = <
0140 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_cts.gpio_150 */
0141 OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */
0142 >;
0143 };
0144
0145 smsc911x_pins: pinmux_smsc911x_pins {
0146 pinctrl-single,pins = <
0147 OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
0148 >;
0149 };
0150 };
0151
0152 &omap3_pmx_wkup {
0153 dss_dpi_pins2: pinmux_dss_dpi_pins1 {
0154 pinctrl-single,pins = <
0155 OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */
0156 OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */
0157 OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */
0158 OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */
0159 OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */
0160 OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */
0161 >;
0162 };
0163 };
0164
0165 &mmc1 {
0166 pinctrl-names = "default";
0167 pinctrl-0 = <&mmc1_pins>;
0168 };
0169
0170 &mmc2 {
0171 pinctrl-names = "default";
0172 pinctrl-0 = <&mmc2_pins>;
0173 };
0174
0175 &mmc3 {
0176 status = "disabled";
0177 };
0178
0179 &uart1 {
0180 interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>;
0181 };
0182
0183 &uart2 {
0184 interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
0185 };
0186
0187 &uart3 {
0188 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
0189 pinctrl-names = "default";
0190 pinctrl-0 = <&uart3_pins>;
0191 };
0192
0193 /*
0194 * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface
0195 * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V.
0196 */
0197 &gpio2 {
0198 en-usb2-port-hog {
0199 gpio-hog;
0200 gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */
0201 output-low;
0202 line-name = "enable usb2 port";
0203 };
0204 };
0205
0206 /* T2_GPIO_2 low to route GPIO_61 to on-board devices */
0207 &twl_gpio {
0208 en_on_board_gpio_61 {
0209 gpio-hog;
0210 gpios = <2 GPIO_ACTIVE_HIGH>;
0211 output-low;
0212 line-name = "en_hsusb2_clk";
0213 };
0214 };
0215
0216 &gpmc {
0217 ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */
0218 <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for LAN9220 */
0219
0220 ethernet@gpmc {
0221 pinctrl-names = "default";
0222 pinctrl-0 = <&smsc911x_pins>;
0223 };
0224 };
