0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for OMAP24xx clock data
0004 *
0005 * Copyright (C) 2014 Texas Instruments, Inc.
0006 */
0007 &scm_clocks {
0008 mcbsp1_mux_fck: mcbsp1_mux_fck@4 {
0009 #clock-cells = <0>;
0010 compatible = "ti,composite-mux-clock";
0011 clocks = <&func_96m_ck>, <&mcbsp_clks>;
0012 ti,bit-shift = <2>;
0013 reg = <0x4>;
0014 };
0015
0016 mcbsp1_fck: mcbsp1_fck {
0017 #clock-cells = <0>;
0018 compatible = "ti,composite-clock";
0019 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
0020 };
0021
0022 mcbsp2_mux_fck: mcbsp2_mux_fck@4 {
0023 #clock-cells = <0>;
0024 compatible = "ti,composite-mux-clock";
0025 clocks = <&func_96m_ck>, <&mcbsp_clks>;
0026 ti,bit-shift = <6>;
0027 reg = <0x4>;
0028 };
0029
0030 mcbsp2_fck: mcbsp2_fck {
0031 #clock-cells = <0>;
0032 compatible = "ti,composite-clock";
0033 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
0034 };
0035 };
0036
0037 &prcm_clocks {
0038 func_32k_ck: func_32k_ck {
0039 #clock-cells = <0>;
0040 compatible = "fixed-clock";
0041 clock-frequency = <32768>;
0042 };
0043
0044 secure_32k_ck: secure_32k_ck {
0045 #clock-cells = <0>;
0046 compatible = "fixed-clock";
0047 clock-frequency = <32768>;
0048 };
0049
0050 virt_12m_ck: virt_12m_ck {
0051 #clock-cells = <0>;
0052 compatible = "fixed-clock";
0053 clock-frequency = <12000000>;
0054 };
0055
0056 virt_13m_ck: virt_13m_ck {
0057 #clock-cells = <0>;
0058 compatible = "fixed-clock";
0059 clock-frequency = <13000000>;
0060 };
0061
0062 virt_19200000_ck: virt_19200000_ck {
0063 #clock-cells = <0>;
0064 compatible = "fixed-clock";
0065 clock-frequency = <19200000>;
0066 };
0067
0068 virt_26m_ck: virt_26m_ck {
0069 #clock-cells = <0>;
0070 compatible = "fixed-clock";
0071 clock-frequency = <26000000>;
0072 };
0073
0074 aplls_clkin_ck: aplls_clkin_ck@540 {
0075 #clock-cells = <0>;
0076 compatible = "ti,mux-clock";
0077 clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
0078 ti,bit-shift = <23>;
0079 reg = <0x0540>;
0080 };
0081
0082 aplls_clkin_x2_ck: aplls_clkin_x2_ck {
0083 #clock-cells = <0>;
0084 compatible = "fixed-factor-clock";
0085 clocks = <&aplls_clkin_ck>;
0086 clock-mult = <2>;
0087 clock-div = <1>;
0088 };
0089
0090 osc_ck: osc_ck@60 {
0091 #clock-cells = <0>;
0092 compatible = "ti,mux-clock";
0093 clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
0094 ti,bit-shift = <6>;
0095 reg = <0x0060>;
0096 ti,index-starts-at-one;
0097 };
0098
0099 sys_ck: sys_ck@60 {
0100 #clock-cells = <0>;
0101 compatible = "ti,divider-clock";
0102 clocks = <&osc_ck>;
0103 ti,bit-shift = <6>;
0104 ti,max-div = <3>;
0105 reg = <0x0060>;
0106 ti,index-starts-at-one;
0107 };
0108
0109 alt_ck: alt_ck {
0110 #clock-cells = <0>;
0111 compatible = "fixed-clock";
0112 clock-frequency = <54000000>;
0113 };
0114
0115 mcbsp_clks: mcbsp_clks {
0116 #clock-cells = <0>;
0117 compatible = "fixed-clock";
0118 clock-frequency = <0x0>;
0119 };
0120
0121 dpll_ck: dpll_ck@500 {
0122 #clock-cells = <0>;
0123 compatible = "ti,omap2-dpll-core-clock";
0124 clocks = <&sys_ck>, <&sys_ck>;
0125 reg = <0x0500>, <0x0540>;
0126 };
0127
0128 apll96_ck: apll96_ck@500 {
0129 #clock-cells = <0>;
0130 compatible = "ti,omap2-apll-clock";
0131 clocks = <&sys_ck>;
0132 ti,bit-shift = <2>;
0133 ti,idlest-shift = <8>;
0134 ti,clock-frequency = <96000000>;
0135 reg = <0x0500>, <0x0530>, <0x0520>;
0136 };
0137
0138 apll54_ck: apll54_ck@500 {
0139 #clock-cells = <0>;
0140 compatible = "ti,omap2-apll-clock";
0141 clocks = <&sys_ck>;
0142 ti,bit-shift = <6>;
0143 ti,idlest-shift = <9>;
0144 ti,clock-frequency = <54000000>;
0145 reg = <0x0500>, <0x0530>, <0x0520>;
0146 };
0147
0148 func_54m_ck: func_54m_ck@540 {
0149 #clock-cells = <0>;
0150 compatible = "ti,mux-clock";
0151 clocks = <&apll54_ck>, <&alt_ck>;
0152 ti,bit-shift = <5>;
0153 reg = <0x0540>;
0154 };
0155
0156 core_ck: core_ck {
0157 #clock-cells = <0>;
0158 compatible = "fixed-factor-clock";
0159 clocks = <&dpll_ck>;
0160 clock-mult = <1>;
0161 clock-div = <1>;
0162 };
0163
0164 func_96m_ck: func_96m_ck@540 {
0165 #clock-cells = <0>;
0166 };
0167
0168 apll96_d2_ck: apll96_d2_ck {
0169 #clock-cells = <0>;
0170 compatible = "fixed-factor-clock";
0171 clocks = <&apll96_ck>;
0172 clock-mult = <1>;
0173 clock-div = <2>;
0174 };
0175
0176 func_48m_ck: func_48m_ck@540 {
0177 #clock-cells = <0>;
0178 compatible = "ti,mux-clock";
0179 clocks = <&apll96_d2_ck>, <&alt_ck>;
0180 ti,bit-shift = <3>;
0181 reg = <0x0540>;
0182 };
0183
0184 func_12m_ck: func_12m_ck {
0185 #clock-cells = <0>;
0186 compatible = "fixed-factor-clock";
0187 clocks = <&func_48m_ck>;
0188 clock-mult = <1>;
0189 clock-div = <4>;
0190 };
0191
0192 sys_clkout_src_gate: sys_clkout_src_gate@70 {
0193 #clock-cells = <0>;
0194 compatible = "ti,composite-no-wait-gate-clock";
0195 clocks = <&core_ck>;
0196 ti,bit-shift = <7>;
0197 reg = <0x0070>;
0198 };
0199
0200 sys_clkout_src_mux: sys_clkout_src_mux@70 {
0201 #clock-cells = <0>;
0202 compatible = "ti,composite-mux-clock";
0203 clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
0204 reg = <0x0070>;
0205 };
0206
0207 sys_clkout_src: sys_clkout_src {
0208 #clock-cells = <0>;
0209 compatible = "ti,composite-clock";
0210 clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>;
0211 };
0212
0213 sys_clkout: sys_clkout@70 {
0214 #clock-cells = <0>;
0215 compatible = "ti,divider-clock";
0216 clocks = <&sys_clkout_src>;
0217 ti,bit-shift = <3>;
0218 ti,max-div = <64>;
0219 reg = <0x0070>;
0220 ti,index-power-of-two;
0221 };
0222
0223 emul_ck: emul_ck@78 {
0224 #clock-cells = <0>;
0225 compatible = "ti,gate-clock";
0226 clocks = <&func_54m_ck>;
0227 ti,bit-shift = <0>;
0228 reg = <0x0078>;
0229 };
0230
0231 mpu_ck: mpu_ck@140 {
0232 #clock-cells = <0>;
0233 compatible = "ti,divider-clock";
0234 clocks = <&core_ck>;
0235 ti,max-div = <31>;
0236 reg = <0x0140>;
0237 ti,index-starts-at-one;
0238 };
0239
0240 dsp_gate_fck: dsp_gate_fck@800 {
0241 #clock-cells = <0>;
0242 compatible = "ti,composite-gate-clock";
0243 clocks = <&core_ck>;
0244 ti,bit-shift = <0>;
0245 reg = <0x0800>;
0246 };
0247
0248 dsp_div_fck: dsp_div_fck@840 {
0249 #clock-cells = <0>;
0250 compatible = "ti,composite-divider-clock";
0251 clocks = <&core_ck>;
0252 reg = <0x0840>;
0253 };
0254
0255 dsp_fck: dsp_fck {
0256 #clock-cells = <0>;
0257 compatible = "ti,composite-clock";
0258 clocks = <&dsp_gate_fck>, <&dsp_div_fck>;
0259 };
0260
0261 core_l3_ck: core_l3_ck@240 {
0262 #clock-cells = <0>;
0263 compatible = "ti,divider-clock";
0264 clocks = <&core_ck>;
0265 ti,max-div = <31>;
0266 reg = <0x0240>;
0267 ti,index-starts-at-one;
0268 };
0269
0270 gfx_3d_gate_fck: gfx_3d_gate_fck@300 {
0271 #clock-cells = <0>;
0272 compatible = "ti,composite-gate-clock";
0273 clocks = <&core_l3_ck>;
0274 ti,bit-shift = <2>;
0275 reg = <0x0300>;
0276 };
0277
0278 gfx_3d_div_fck: gfx_3d_div_fck@340 {
0279 #clock-cells = <0>;
0280 compatible = "ti,composite-divider-clock";
0281 clocks = <&core_l3_ck>;
0282 ti,max-div = <4>;
0283 reg = <0x0340>;
0284 ti,index-starts-at-one;
0285 };
0286
0287 gfx_3d_fck: gfx_3d_fck {
0288 #clock-cells = <0>;
0289 compatible = "ti,composite-clock";
0290 clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>;
0291 };
0292
0293 gfx_2d_gate_fck: gfx_2d_gate_fck@300 {
0294 #clock-cells = <0>;
0295 compatible = "ti,composite-gate-clock";
0296 clocks = <&core_l3_ck>;
0297 ti,bit-shift = <1>;
0298 reg = <0x0300>;
0299 };
0300
0301 gfx_2d_div_fck: gfx_2d_div_fck@340 {
0302 #clock-cells = <0>;
0303 compatible = "ti,composite-divider-clock";
0304 clocks = <&core_l3_ck>;
0305 ti,max-div = <4>;
0306 reg = <0x0340>;
0307 ti,index-starts-at-one;
0308 };
0309
0310 gfx_2d_fck: gfx_2d_fck {
0311 #clock-cells = <0>;
0312 compatible = "ti,composite-clock";
0313 clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>;
0314 };
0315
0316 gfx_ick: gfx_ick@310 {
0317 #clock-cells = <0>;
0318 compatible = "ti,wait-gate-clock";
0319 clocks = <&core_l3_ck>;
0320 ti,bit-shift = <0>;
0321 reg = <0x0310>;
0322 };
0323
0324 l4_ck: l4_ck@240 {
0325 #clock-cells = <0>;
0326 compatible = "ti,divider-clock";
0327 clocks = <&core_l3_ck>;
0328 ti,bit-shift = <5>;
0329 ti,max-div = <3>;
0330 reg = <0x0240>;
0331 ti,index-starts-at-one;
0332 };
0333
0334 dss_ick: dss_ick@210 {
0335 #clock-cells = <0>;
0336 compatible = "ti,omap3-no-wait-interface-clock";
0337 clocks = <&l4_ck>;
0338 ti,bit-shift = <0>;
0339 reg = <0x0210>;
0340 };
0341
0342 dss1_gate_fck: dss1_gate_fck@200 {
0343 #clock-cells = <0>;
0344 compatible = "ti,composite-no-wait-gate-clock";
0345 clocks = <&core_ck>;
0346 ti,bit-shift = <0>;
0347 reg = <0x0200>;
0348 };
0349
0350 core_d2_ck: core_d2_ck {
0351 #clock-cells = <0>;
0352 compatible = "fixed-factor-clock";
0353 clocks = <&core_ck>;
0354 clock-mult = <1>;
0355 clock-div = <2>;
0356 };
0357
0358 core_d3_ck: core_d3_ck {
0359 #clock-cells = <0>;
0360 compatible = "fixed-factor-clock";
0361 clocks = <&core_ck>;
0362 clock-mult = <1>;
0363 clock-div = <3>;
0364 };
0365
0366 core_d4_ck: core_d4_ck {
0367 #clock-cells = <0>;
0368 compatible = "fixed-factor-clock";
0369 clocks = <&core_ck>;
0370 clock-mult = <1>;
0371 clock-div = <4>;
0372 };
0373
0374 core_d5_ck: core_d5_ck {
0375 #clock-cells = <0>;
0376 compatible = "fixed-factor-clock";
0377 clocks = <&core_ck>;
0378 clock-mult = <1>;
0379 clock-div = <5>;
0380 };
0381
0382 core_d6_ck: core_d6_ck {
0383 #clock-cells = <0>;
0384 compatible = "fixed-factor-clock";
0385 clocks = <&core_ck>;
0386 clock-mult = <1>;
0387 clock-div = <6>;
0388 };
0389
0390 dummy_ck: dummy_ck {
0391 #clock-cells = <0>;
0392 compatible = "fixed-clock";
0393 clock-frequency = <0>;
0394 };
0395
0396 core_d8_ck: core_d8_ck {
0397 #clock-cells = <0>;
0398 compatible = "fixed-factor-clock";
0399 clocks = <&core_ck>;
0400 clock-mult = <1>;
0401 clock-div = <8>;
0402 };
0403
0404 core_d9_ck: core_d9_ck {
0405 #clock-cells = <0>;
0406 compatible = "fixed-factor-clock";
0407 clocks = <&core_ck>;
0408 clock-mult = <1>;
0409 clock-div = <9>;
0410 };
0411
0412 core_d12_ck: core_d12_ck {
0413 #clock-cells = <0>;
0414 compatible = "fixed-factor-clock";
0415 clocks = <&core_ck>;
0416 clock-mult = <1>;
0417 clock-div = <12>;
0418 };
0419
0420 core_d16_ck: core_d16_ck {
0421 #clock-cells = <0>;
0422 compatible = "fixed-factor-clock";
0423 clocks = <&core_ck>;
0424 clock-mult = <1>;
0425 clock-div = <16>;
0426 };
0427
0428 dss1_mux_fck: dss1_mux_fck@240 {
0429 #clock-cells = <0>;
0430 compatible = "ti,composite-mux-clock";
0431 clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>;
0432 ti,bit-shift = <8>;
0433 reg = <0x0240>;
0434 };
0435
0436 dss1_fck: dss1_fck {
0437 #clock-cells = <0>;
0438 compatible = "ti,composite-clock";
0439 clocks = <&dss1_gate_fck>, <&dss1_mux_fck>;
0440 };
0441
0442 dss2_gate_fck: dss2_gate_fck@200 {
0443 #clock-cells = <0>;
0444 compatible = "ti,composite-no-wait-gate-clock";
0445 clocks = <&func_48m_ck>;
0446 ti,bit-shift = <1>;
0447 reg = <0x0200>;
0448 };
0449
0450 dss2_mux_fck: dss2_mux_fck@240 {
0451 #clock-cells = <0>;
0452 compatible = "ti,composite-mux-clock";
0453 clocks = <&sys_ck>, <&func_48m_ck>;
0454 ti,bit-shift = <13>;
0455 reg = <0x0240>;
0456 };
0457
0458 dss2_fck: dss2_fck {
0459 #clock-cells = <0>;
0460 compatible = "ti,composite-clock";
0461 clocks = <&dss2_gate_fck>, <&dss2_mux_fck>;
0462 };
0463
0464 dss_54m_fck: dss_54m_fck@200 {
0465 #clock-cells = <0>;
0466 compatible = "ti,wait-gate-clock";
0467 clocks = <&func_54m_ck>;
0468 ti,bit-shift = <2>;
0469 reg = <0x0200>;
0470 };
0471
0472 ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck@204 {
0473 #clock-cells = <0>;
0474 compatible = "ti,composite-gate-clock";
0475 clocks = <&core_ck>;
0476 ti,bit-shift = <1>;
0477 reg = <0x0204>;
0478 };
0479
0480 ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck@240 {
0481 #clock-cells = <0>;
0482 compatible = "ti,composite-divider-clock";
0483 clocks = <&core_ck>;
0484 ti,bit-shift = <20>;
0485 reg = <0x0240>;
0486 };
0487
0488 ssi_ssr_sst_fck: ssi_ssr_sst_fck {
0489 #clock-cells = <0>;
0490 compatible = "ti,composite-clock";
0491 clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>;
0492 };
0493
0494 usb_l4_gate_ick: usb_l4_gate_ick@214 {
0495 #clock-cells = <0>;
0496 compatible = "ti,composite-interface-clock";
0497 clocks = <&core_l3_ck>;
0498 ti,bit-shift = <0>;
0499 reg = <0x0214>;
0500 };
0501
0502 usb_l4_div_ick: usb_l4_div_ick@240 {
0503 #clock-cells = <0>;
0504 compatible = "ti,composite-divider-clock";
0505 clocks = <&core_l3_ck>;
0506 ti,bit-shift = <25>;
0507 reg = <0x0240>;
0508 ti,dividers = <0>, <1>, <2>, <0>, <4>;
0509 };
0510
0511 usb_l4_ick: usb_l4_ick {
0512 #clock-cells = <0>;
0513 compatible = "ti,composite-clock";
0514 clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
0515 };
0516
0517 ssi_l4_ick: ssi_l4_ick@214 {
0518 #clock-cells = <0>;
0519 compatible = "ti,omap3-interface-clock";
0520 clocks = <&l4_ck>;
0521 ti,bit-shift = <1>;
0522 reg = <0x0214>;
0523 };
0524
0525 gpt1_ick: gpt1_ick@410 {
0526 #clock-cells = <0>;
0527 compatible = "ti,omap3-interface-clock";
0528 clocks = <&sys_ck>;
0529 ti,bit-shift = <0>;
0530 reg = <0x0410>;
0531 };
0532
0533 gpt1_gate_fck: gpt1_gate_fck@400 {
0534 #clock-cells = <0>;
0535 compatible = "ti,composite-gate-clock";
0536 clocks = <&func_32k_ck>;
0537 ti,bit-shift = <0>;
0538 reg = <0x0400>;
0539 };
0540
0541 gpt1_mux_fck: gpt1_mux_fck@440 {
0542 #clock-cells = <0>;
0543 compatible = "ti,composite-mux-clock";
0544 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
0545 reg = <0x0440>;
0546 };
0547
0548 gpt1_fck: gpt1_fck {
0549 #clock-cells = <0>;
0550 compatible = "ti,composite-clock";
0551 clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
0552 };
0553
0554 gpt2_ick: gpt2_ick@210 {
0555 #clock-cells = <0>;
0556 compatible = "ti,omap3-interface-clock";
0557 clocks = <&l4_ck>;
0558 ti,bit-shift = <4>;
0559 reg = <0x0210>;
0560 };
0561
0562 gpt2_gate_fck: gpt2_gate_fck@200 {
0563 #clock-cells = <0>;
0564 compatible = "ti,composite-gate-clock";
0565 clocks = <&func_32k_ck>;
0566 ti,bit-shift = <4>;
0567 reg = <0x0200>;
0568 };
0569
0570 gpt2_mux_fck: gpt2_mux_fck@244 {
0571 #clock-cells = <0>;
0572 compatible = "ti,composite-mux-clock";
0573 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
0574 ti,bit-shift = <2>;
0575 reg = <0x0244>;
0576 };
0577
0578 gpt2_fck: gpt2_fck {
0579 #clock-cells = <0>;
0580 compatible = "ti,composite-clock";
0581 clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
0582 };
0583
0584 gpt3_ick: gpt3_ick@210 {
0585 #clock-cells = <0>;
0586 compatible = "ti,omap3-interface-clock";
0587 clocks = <&l4_ck>;
0588 ti,bit-shift = <5>;
0589 reg = <0x0210>;
0590 };
0591
0592 gpt3_gate_fck: gpt3_gate_fck@200 {
0593 #clock-cells = <0>;
0594 compatible = "ti,composite-gate-clock";
0595 clocks = <&func_32k_ck>;
0596 ti,bit-shift = <5>;
0597 reg = <0x0200>;
0598 };
0599
0600 gpt3_mux_fck: gpt3_mux_fck@244 {
0601 #clock-cells = <0>;
0602 compatible = "ti,composite-mux-clock";
0603 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
0604 ti,bit-shift = <4>;
0605 reg = <0x0244>;
0606 };
0607
0608 gpt3_fck: gpt3_fck {
0609 #clock-cells = <0>;
0610 compatible = "ti,composite-clock";
0611 clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
0612 };
0613
0614 gpt4_ick: gpt4_ick@210 {
0615 #clock-cells = <0>;
0616 compatible = "ti,omap3-interface-clock";
0617 clocks = <&l4_ck>;
0618 ti,bit-shift = <6>;
0619 reg = <0x0210>;
0620 };
0621
0622 gpt4_gate_fck: gpt4_gate_fck@200 {
0623 #clock-cells = <0>;
0624 compatible = "ti,composite-gate-clock";
0625 clocks = <&func_32k_ck>;
0626 ti,bit-shift = <6>;
0627 reg = <0x0200>;
0628 };
0629
0630 gpt4_mux_fck: gpt4_mux_fck@244 {
0631 #clock-cells = <0>;
0632 compatible = "ti,composite-mux-clock";
0633 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
0634 ti,bit-shift = <6>;
0635 reg = <0x0244>;
0636 };
0637
0638 gpt4_fck: gpt4_fck {
0639 #clock-cells = <0>;
0640 compatible = "ti,composite-clock";
0641 clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
0642 };
0643
0644 gpt5_ick: gpt5_ick@210 {
0645 #clock-cells = <0>;
0646 compatible = "ti,omap3-interface-clock";
0647 clocks = <&l4_ck>;
0648 ti,bit-shift = <7>;
0649 reg = <0x0210>;
0650 };
0651
0652 gpt5_gate_fck: gpt5_gate_fck@200 {
0653 #clock-cells = <0>;
0654 compatible = "ti,composite-gate-clock";
0655 clocks = <&func_32k_ck>;
0656 ti,bit-shift = <7>;
0657 reg = <0x0200>;
0658 };
0659
0660 gpt5_mux_fck: gpt5_mux_fck@244 {
0661 #clock-cells = <0>;
0662 compatible = "ti,composite-mux-clock";
0663 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
0664 ti,bit-shift = <8>;
0665 reg = <0x0244>;
0666 };
0667
0668 gpt5_fck: gpt5_fck {
0669 #clock-cells = <0>;
0670 compatible = "ti,composite-clock";
0671 clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
0672 };
0673
0674 gpt6_ick: gpt6_ick@210 {
0675 #clock-cells = <0>;
0676 compatible = "ti,omap3-interface-clock";
0677 clocks = <&l4_ck>;
0678 ti,bit-shift = <8>;
0679 reg = <0x0210>;
0680 };
0681
0682 gpt6_gate_fck: gpt6_gate_fck@200 {
0683 #clock-cells = <0>;
0684 compatible = "ti,composite-gate-clock";
0685 clocks = <&func_32k_ck>;
0686 ti,bit-shift = <8>;
0687 reg = <0x0200>;
0688 };
0689
0690 gpt6_mux_fck: gpt6_mux_fck@244 {
0691 #clock-cells = <0>;
0692 compatible = "ti,composite-mux-clock";
0693 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
0694 ti,bit-shift = <10>;
0695 reg = <0x0244>;
0696 };
0697
0698 gpt6_fck: gpt6_fck {
0699 #clock-cells = <0>;
0700 compatible = "ti,composite-clock";
0701 clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
0702 };
0703
0704 gpt7_ick: gpt7_ick@210 {
0705 #clock-cells = <0>;
0706 compatible = "ti,omap3-interface-clock";
0707 clocks = <&l4_ck>;
0708 ti,bit-shift = <9>;
0709 reg = <0x0210>;
0710 };
0711
0712 gpt7_gate_fck: gpt7_gate_fck@200 {
0713 #clock-cells = <0>;
0714 compatible = "ti,composite-gate-clock";
0715 clocks = <&func_32k_ck>;
0716 ti,bit-shift = <9>;
0717 reg = <0x0200>;
0718 };
0719
0720 gpt7_mux_fck: gpt7_mux_fck@244 {
0721 #clock-cells = <0>;
0722 compatible = "ti,composite-mux-clock";
0723 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
0724 ti,bit-shift = <12>;
0725 reg = <0x0244>;
0726 };
0727
0728 gpt7_fck: gpt7_fck {
0729 #clock-cells = <0>;
0730 compatible = "ti,composite-clock";
0731 clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
0732 };
0733
0734 gpt8_ick: gpt8_ick@210 {
0735 #clock-cells = <0>;
0736 compatible = "ti,omap3-interface-clock";
0737 clocks = <&l4_ck>;
0738 ti,bit-shift = <10>;
0739 reg = <0x0210>;
0740 };
0741
0742 gpt8_gate_fck: gpt8_gate_fck@200 {
0743 #clock-cells = <0>;
0744 compatible = "ti,composite-gate-clock";
0745 clocks = <&func_32k_ck>;
0746 ti,bit-shift = <10>;
0747 reg = <0x0200>;
0748 };
0749
0750 gpt8_mux_fck: gpt8_mux_fck@244 {
0751 #clock-cells = <0>;
0752 compatible = "ti,composite-mux-clock";
0753 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
0754 ti,bit-shift = <14>;
0755 reg = <0x0244>;
0756 };
0757
0758 gpt8_fck: gpt8_fck {
0759 #clock-cells = <0>;
0760 compatible = "ti,composite-clock";
0761 clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
0762 };
0763
0764 gpt9_ick: gpt9_ick@210 {
0765 #clock-cells = <0>;
0766 compatible = "ti,omap3-interface-clock";
0767 clocks = <&l4_ck>;
0768 ti,bit-shift = <11>;
0769 reg = <0x0210>;
0770 };
0771
0772 gpt9_gate_fck: gpt9_gate_fck@200 {
0773 #clock-cells = <0>;
0774 compatible = "ti,composite-gate-clock";
0775 clocks = <&func_32k_ck>;
0776 ti,bit-shift = <11>;
0777 reg = <0x0200>;
0778 };
0779
0780 gpt9_mux_fck: gpt9_mux_fck@244 {
0781 #clock-cells = <0>;
0782 compatible = "ti,composite-mux-clock";
0783 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
0784 ti,bit-shift = <16>;
0785 reg = <0x0244>;
0786 };
0787
0788 gpt9_fck: gpt9_fck {
0789 #clock-cells = <0>;
0790 compatible = "ti,composite-clock";
0791 clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
0792 };
0793
0794 gpt10_ick: gpt10_ick@210 {
0795 #clock-cells = <0>;
0796 compatible = "ti,omap3-interface-clock";
0797 clocks = <&l4_ck>;
0798 ti,bit-shift = <12>;
0799 reg = <0x0210>;
0800 };
0801
0802 gpt10_gate_fck: gpt10_gate_fck@200 {
0803 #clock-cells = <0>;
0804 compatible = "ti,composite-gate-clock";
0805 clocks = <&func_32k_ck>;
0806 ti,bit-shift = <12>;
0807 reg = <0x0200>;
0808 };
0809
0810 gpt10_mux_fck: gpt10_mux_fck@244 {
0811 #clock-cells = <0>;
0812 compatible = "ti,composite-mux-clock";
0813 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
0814 ti,bit-shift = <18>;
0815 reg = <0x0244>;
0816 };
0817
0818 gpt10_fck: gpt10_fck {
0819 #clock-cells = <0>;
0820 compatible = "ti,composite-clock";
0821 clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
0822 };
0823
0824 gpt11_ick: gpt11_ick@210 {
0825 #clock-cells = <0>;
0826 compatible = "ti,omap3-interface-clock";
0827 clocks = <&l4_ck>;
0828 ti,bit-shift = <13>;
0829 reg = <0x0210>;
0830 };
0831
0832 gpt11_gate_fck: gpt11_gate_fck@200 {
0833 #clock-cells = <0>;
0834 compatible = "ti,composite-gate-clock";
0835 clocks = <&func_32k_ck>;
0836 ti,bit-shift = <13>;
0837 reg = <0x0200>;
0838 };
0839
0840 gpt11_mux_fck: gpt11_mux_fck@244 {
0841 #clock-cells = <0>;
0842 compatible = "ti,composite-mux-clock";
0843 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
0844 ti,bit-shift = <20>;
0845 reg = <0x0244>;
0846 };
0847
0848 gpt11_fck: gpt11_fck {
0849 #clock-cells = <0>;
0850 compatible = "ti,composite-clock";
0851 clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
0852 };
0853
0854 gpt12_ick: gpt12_ick@210 {
0855 #clock-cells = <0>;
0856 compatible = "ti,omap3-interface-clock";
0857 clocks = <&l4_ck>;
0858 ti,bit-shift = <14>;
0859 reg = <0x0210>;
0860 };
0861
0862 gpt12_gate_fck: gpt12_gate_fck@200 {
0863 #clock-cells = <0>;
0864 compatible = "ti,composite-gate-clock";
0865 clocks = <&func_32k_ck>;
0866 ti,bit-shift = <14>;
0867 reg = <0x0200>;
0868 };
0869
0870 gpt12_mux_fck: gpt12_mux_fck@244 {
0871 #clock-cells = <0>;
0872 compatible = "ti,composite-mux-clock";
0873 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
0874 ti,bit-shift = <22>;
0875 reg = <0x0244>;
0876 };
0877
0878 gpt12_fck: gpt12_fck {
0879 #clock-cells = <0>;
0880 compatible = "ti,composite-clock";
0881 clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>;
0882 };
0883
0884 mcbsp1_ick: mcbsp1_ick@210 {
0885 #clock-cells = <0>;
0886 compatible = "ti,omap3-interface-clock";
0887 clocks = <&l4_ck>;
0888 ti,bit-shift = <15>;
0889 reg = <0x0210>;
0890 };
0891
0892 mcbsp1_gate_fck: mcbsp1_gate_fck@200 {
0893 #clock-cells = <0>;
0894 compatible = "ti,composite-gate-clock";
0895 clocks = <&mcbsp_clks>;
0896 ti,bit-shift = <15>;
0897 reg = <0x0200>;
0898 };
0899
0900 mcbsp2_ick: mcbsp2_ick@210 {
0901 #clock-cells = <0>;
0902 compatible = "ti,omap3-interface-clock";
0903 clocks = <&l4_ck>;
0904 ti,bit-shift = <16>;
0905 reg = <0x0210>;
0906 };
0907
0908 mcbsp2_gate_fck: mcbsp2_gate_fck@200 {
0909 #clock-cells = <0>;
0910 compatible = "ti,composite-gate-clock";
0911 clocks = <&mcbsp_clks>;
0912 ti,bit-shift = <16>;
0913 reg = <0x0200>;
0914 };
0915
0916 mcspi1_ick: mcspi1_ick@210 {
0917 #clock-cells = <0>;
0918 compatible = "ti,omap3-interface-clock";
0919 clocks = <&l4_ck>;
0920 ti,bit-shift = <17>;
0921 reg = <0x0210>;
0922 };
0923
0924 mcspi1_fck: mcspi1_fck@200 {
0925 #clock-cells = <0>;
0926 compatible = "ti,wait-gate-clock";
0927 clocks = <&func_48m_ck>;
0928 ti,bit-shift = <17>;
0929 reg = <0x0200>;
0930 };
0931
0932 mcspi2_ick: mcspi2_ick@210 {
0933 #clock-cells = <0>;
0934 compatible = "ti,omap3-interface-clock";
0935 clocks = <&l4_ck>;
0936 ti,bit-shift = <18>;
0937 reg = <0x0210>;
0938 };
0939
0940 mcspi2_fck: mcspi2_fck@200 {
0941 #clock-cells = <0>;
0942 compatible = "ti,wait-gate-clock";
0943 clocks = <&func_48m_ck>;
0944 ti,bit-shift = <18>;
0945 reg = <0x0200>;
0946 };
0947
0948 uart1_ick: uart1_ick@210 {
0949 #clock-cells = <0>;
0950 compatible = "ti,omap3-interface-clock";
0951 clocks = <&l4_ck>;
0952 ti,bit-shift = <21>;
0953 reg = <0x0210>;
0954 };
0955
0956 uart1_fck: uart1_fck@200 {
0957 #clock-cells = <0>;
0958 compatible = "ti,wait-gate-clock";
0959 clocks = <&func_48m_ck>;
0960 ti,bit-shift = <21>;
0961 reg = <0x0200>;
0962 };
0963
0964 uart2_ick: uart2_ick@210 {
0965 #clock-cells = <0>;
0966 compatible = "ti,omap3-interface-clock";
0967 clocks = <&l4_ck>;
0968 ti,bit-shift = <22>;
0969 reg = <0x0210>;
0970 };
0971
0972 uart2_fck: uart2_fck@200 {
0973 #clock-cells = <0>;
0974 compatible = "ti,wait-gate-clock";
0975 clocks = <&func_48m_ck>;
0976 ti,bit-shift = <22>;
0977 reg = <0x0200>;
0978 };
0979
0980 uart3_ick: uart3_ick@214 {
0981 #clock-cells = <0>;
0982 compatible = "ti,omap3-interface-clock";
0983 clocks = <&l4_ck>;
0984 ti,bit-shift = <2>;
0985 reg = <0x0214>;
0986 };
0987
0988 uart3_fck: uart3_fck@204 {
0989 #clock-cells = <0>;
0990 compatible = "ti,wait-gate-clock";
0991 clocks = <&func_48m_ck>;
0992 ti,bit-shift = <2>;
0993 reg = <0x0204>;
0994 };
0995
0996 gpios_ick: gpios_ick@410 {
0997 #clock-cells = <0>;
0998 compatible = "ti,omap3-interface-clock";
0999 clocks = <&sys_ck>;
1000 ti,bit-shift = <2>;
1001 reg = <0x0410>;
1002 };
1003
1004 gpios_fck: gpios_fck@400 {
1005 #clock-cells = <0>;
1006 compatible = "ti,wait-gate-clock";
1007 clocks = <&func_32k_ck>;
1008 ti,bit-shift = <2>;
1009 reg = <0x0400>;
1010 };
1011
1012 mpu_wdt_ick: mpu_wdt_ick@410 {
1013 #clock-cells = <0>;
1014 compatible = "ti,omap3-interface-clock";
1015 clocks = <&sys_ck>;
1016 ti,bit-shift = <3>;
1017 reg = <0x0410>;
1018 };
1019
1020 mpu_wdt_fck: mpu_wdt_fck@400 {
1021 #clock-cells = <0>;
1022 compatible = "ti,wait-gate-clock";
1023 clocks = <&func_32k_ck>;
1024 ti,bit-shift = <3>;
1025 reg = <0x0400>;
1026 };
1027
1028 sync_32k_ick: sync_32k_ick@410 {
1029 #clock-cells = <0>;
1030 compatible = "ti,omap3-interface-clock";
1031 clocks = <&sys_ck>;
1032 ti,bit-shift = <1>;
1033 reg = <0x0410>;
1034 };
1035
1036 wdt1_ick: wdt1_ick@410 {
1037 #clock-cells = <0>;
1038 compatible = "ti,omap3-interface-clock";
1039 clocks = <&sys_ck>;
1040 ti,bit-shift = <4>;
1041 reg = <0x0410>;
1042 };
1043
1044 omapctrl_ick: omapctrl_ick@410 {
1045 #clock-cells = <0>;
1046 compatible = "ti,omap3-interface-clock";
1047 clocks = <&sys_ck>;
1048 ti,bit-shift = <5>;
1049 reg = <0x0410>;
1050 };
1051
1052 cam_fck: cam_fck@200 {
1053 #clock-cells = <0>;
1054 compatible = "ti,gate-clock";
1055 clocks = <&func_96m_ck>;
1056 ti,bit-shift = <31>;
1057 reg = <0x0200>;
1058 };
1059
1060 cam_ick: cam_ick@210 {
1061 #clock-cells = <0>;
1062 compatible = "ti,omap3-no-wait-interface-clock";
1063 clocks = <&l4_ck>;
1064 ti,bit-shift = <31>;
1065 reg = <0x0210>;
1066 };
1067
1068 mailboxes_ick: mailboxes_ick@210 {
1069 #clock-cells = <0>;
1070 compatible = "ti,omap3-interface-clock";
1071 clocks = <&l4_ck>;
1072 ti,bit-shift = <30>;
1073 reg = <0x0210>;
1074 };
1075
1076 wdt4_ick: wdt4_ick@210 {
1077 #clock-cells = <0>;
1078 compatible = "ti,omap3-interface-clock";
1079 clocks = <&l4_ck>;
1080 ti,bit-shift = <29>;
1081 reg = <0x0210>;
1082 };
1083
1084 wdt4_fck: wdt4_fck@200 {
1085 #clock-cells = <0>;
1086 compatible = "ti,wait-gate-clock";
1087 clocks = <&func_32k_ck>;
1088 ti,bit-shift = <29>;
1089 reg = <0x0200>;
1090 };
1091
1092 mspro_ick: mspro_ick@210 {
1093 #clock-cells = <0>;
1094 compatible = "ti,omap3-interface-clock";
1095 clocks = <&l4_ck>;
1096 ti,bit-shift = <27>;
1097 reg = <0x0210>;
1098 };
1099
1100 mspro_fck: mspro_fck@200 {
1101 #clock-cells = <0>;
1102 compatible = "ti,wait-gate-clock";
1103 clocks = <&func_96m_ck>;
1104 ti,bit-shift = <27>;
1105 reg = <0x0200>;
1106 };
1107
1108 fac_ick: fac_ick@210 {
1109 #clock-cells = <0>;
1110 compatible = "ti,omap3-interface-clock";
1111 clocks = <&l4_ck>;
1112 ti,bit-shift = <25>;
1113 reg = <0x0210>;
1114 };
1115
1116 fac_fck: fac_fck@200 {
1117 #clock-cells = <0>;
1118 compatible = "ti,wait-gate-clock";
1119 clocks = <&func_12m_ck>;
1120 ti,bit-shift = <25>;
1121 reg = <0x0200>;
1122 };
1123
1124 hdq_ick: hdq_ick@210 {
1125 #clock-cells = <0>;
1126 compatible = "ti,omap3-interface-clock";
1127 clocks = <&l4_ck>;
1128 ti,bit-shift = <23>;
1129 reg = <0x0210>;
1130 };
1131
1132 hdq_fck: hdq_fck@200 {
1133 #clock-cells = <0>;
1134 compatible = "ti,wait-gate-clock";
1135 clocks = <&func_12m_ck>;
1136 ti,bit-shift = <23>;
1137 reg = <0x0200>;
1138 };
1139
1140 i2c1_ick: i2c1_ick@210 {
1141 #clock-cells = <0>;
1142 compatible = "ti,omap3-interface-clock";
1143 clocks = <&l4_ck>;
1144 ti,bit-shift = <19>;
1145 reg = <0x0210>;
1146 };
1147
1148 i2c2_ick: i2c2_ick@210 {
1149 #clock-cells = <0>;
1150 compatible = "ti,omap3-interface-clock";
1151 clocks = <&l4_ck>;
1152 ti,bit-shift = <20>;
1153 reg = <0x0210>;
1154 };
1155
1156 gpmc_fck: gpmc_fck@238 {
1157 #clock-cells = <0>;
1158 compatible = "ti,fixed-factor-clock";
1159 clocks = <&core_l3_ck>;
1160 ti,clock-div = <1>;
1161 ti,autoidle-shift = <1>;
1162 reg = <0x0238>;
1163 ti,clock-mult = <1>;
1164 };
1165
1166 sdma_fck: sdma_fck {
1167 #clock-cells = <0>;
1168 compatible = "fixed-factor-clock";
1169 clocks = <&core_l3_ck>;
1170 clock-mult = <1>;
1171 clock-div = <1>;
1172 };
1173
1174 sdma_ick: sdma_ick@238 {
1175 #clock-cells = <0>;
1176 compatible = "ti,fixed-factor-clock";
1177 clocks = <&core_l3_ck>;
1178 ti,clock-div = <1>;
1179 ti,autoidle-shift = <0>;
1180 reg = <0x0238>;
1181 ti,clock-mult = <1>;
1182 };
1183
1184 sdrc_ick: sdrc_ick@238 {
1185 #clock-cells = <0>;
1186 compatible = "ti,fixed-factor-clock";
1187 clocks = <&core_l3_ck>;
1188 ti,clock-div = <1>;
1189 ti,autoidle-shift = <2>;
1190 reg = <0x0238>;
1191 ti,clock-mult = <1>;
1192 };
1193
1194 des_ick: des_ick@21c {
1195 #clock-cells = <0>;
1196 compatible = "ti,omap3-interface-clock";
1197 clocks = <&l4_ck>;
1198 ti,bit-shift = <0>;
1199 reg = <0x021c>;
1200 };
1201
1202 sha_ick: sha_ick@21c {
1203 #clock-cells = <0>;
1204 compatible = "ti,omap3-interface-clock";
1205 clocks = <&l4_ck>;
1206 ti,bit-shift = <1>;
1207 reg = <0x021c>;
1208 };
1209
1210 rng_ick: rng_ick@21c {
1211 #clock-cells = <0>;
1212 compatible = "ti,omap3-interface-clock";
1213 clocks = <&l4_ck>;
1214 ti,bit-shift = <2>;
1215 reg = <0x021c>;
1216 };
1217
1218 aes_ick: aes_ick@21c {
1219 #clock-cells = <0>;
1220 compatible = "ti,omap3-interface-clock";
1221 clocks = <&l4_ck>;
1222 ti,bit-shift = <3>;
1223 reg = <0x021c>;
1224 };
1225
1226 pka_ick: pka_ick@21c {
1227 #clock-cells = <0>;
1228 compatible = "ti,omap3-interface-clock";
1229 clocks = <&l4_ck>;
1230 ti,bit-shift = <4>;
1231 reg = <0x021c>;
1232 };
1233
1234 usb_fck: usb_fck@204 {
1235 #clock-cells = <0>;
1236 compatible = "ti,wait-gate-clock";
1237 clocks = <&func_48m_ck>;
1238 ti,bit-shift = <0>;
1239 reg = <0x0204>;
1240 };
1241 };
