0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for OMAP2430 clock data
0004 *
0005 * Copyright (C) 2014 Texas Instruments, Inc.
0006 */
0007
0008 &scm_clocks {
0009 mcbsp3_mux_fck: mcbsp3_mux_fck@78 {
0010 #clock-cells = <0>;
0011 compatible = "ti,composite-mux-clock";
0012 clocks = <&func_96m_ck>, <&mcbsp_clks>;
0013 reg = <0x78>;
0014 };
0015
0016 mcbsp3_fck: mcbsp3_fck {
0017 #clock-cells = <0>;
0018 compatible = "ti,composite-clock";
0019 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
0020 };
0021
0022 mcbsp4_mux_fck: mcbsp4_mux_fck@78 {
0023 #clock-cells = <0>;
0024 compatible = "ti,composite-mux-clock";
0025 clocks = <&func_96m_ck>, <&mcbsp_clks>;
0026 ti,bit-shift = <2>;
0027 reg = <0x78>;
0028 };
0029
0030 mcbsp4_fck: mcbsp4_fck {
0031 #clock-cells = <0>;
0032 compatible = "ti,composite-clock";
0033 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
0034 };
0035
0036 mcbsp5_mux_fck: mcbsp5_mux_fck@78 {
0037 #clock-cells = <0>;
0038 compatible = "ti,composite-mux-clock";
0039 clocks = <&func_96m_ck>, <&mcbsp_clks>;
0040 ti,bit-shift = <4>;
0041 reg = <0x78>;
0042 };
0043
0044 mcbsp5_fck: mcbsp5_fck {
0045 #clock-cells = <0>;
0046 compatible = "ti,composite-clock";
0047 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
0048 };
0049 };
0050
0051 &prcm_clocks {
0052 iva2_1_gate_ick: iva2_1_gate_ick@800 {
0053 #clock-cells = <0>;
0054 compatible = "ti,composite-gate-clock";
0055 clocks = <&dsp_fck>;
0056 ti,bit-shift = <0>;
0057 reg = <0x0800>;
0058 };
0059
0060 iva2_1_div_ick: iva2_1_div_ick@840 {
0061 #clock-cells = <0>;
0062 compatible = "ti,composite-divider-clock";
0063 clocks = <&dsp_fck>;
0064 ti,bit-shift = <5>;
0065 ti,max-div = <3>;
0066 reg = <0x0840>;
0067 ti,index-starts-at-one;
0068 };
0069
0070 iva2_1_ick: iva2_1_ick {
0071 #clock-cells = <0>;
0072 compatible = "ti,composite-clock";
0073 clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
0074 };
0075
0076 mdm_gate_ick: mdm_gate_ick@c10 {
0077 #clock-cells = <0>;
0078 compatible = "ti,composite-interface-clock";
0079 clocks = <&core_ck>;
0080 ti,bit-shift = <0>;
0081 reg = <0x0c10>;
0082 };
0083
0084 mdm_div_ick: mdm_div_ick@c40 {
0085 #clock-cells = <0>;
0086 compatible = "ti,composite-divider-clock";
0087 clocks = <&core_ck>;
0088 reg = <0x0c40>;
0089 ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>;
0090 };
0091
0092 mdm_ick: mdm_ick {
0093 #clock-cells = <0>;
0094 compatible = "ti,composite-clock";
0095 clocks = <&mdm_gate_ick>, <&mdm_div_ick>;
0096 };
0097
0098 mdm_osc_ck: mdm_osc_ck@c00 {
0099 #clock-cells = <0>;
0100 compatible = "ti,omap3-interface-clock";
0101 clocks = <&osc_ck>;
0102 ti,bit-shift = <1>;
0103 reg = <0x0c00>;
0104 };
0105
0106 mcbsp3_ick: mcbsp3_ick@214 {
0107 #clock-cells = <0>;
0108 compatible = "ti,omap3-interface-clock";
0109 clocks = <&l4_ck>;
0110 ti,bit-shift = <3>;
0111 reg = <0x0214>;
0112 };
0113
0114 mcbsp3_gate_fck: mcbsp3_gate_fck@204 {
0115 #clock-cells = <0>;
0116 compatible = "ti,composite-gate-clock";
0117 clocks = <&mcbsp_clks>;
0118 ti,bit-shift = <3>;
0119 reg = <0x0204>;
0120 };
0121
0122 mcbsp4_ick: mcbsp4_ick@214 {
0123 #clock-cells = <0>;
0124 compatible = "ti,omap3-interface-clock";
0125 clocks = <&l4_ck>;
0126 ti,bit-shift = <4>;
0127 reg = <0x0214>;
0128 };
0129
0130 mcbsp4_gate_fck: mcbsp4_gate_fck@204 {
0131 #clock-cells = <0>;
0132 compatible = "ti,composite-gate-clock";
0133 clocks = <&mcbsp_clks>;
0134 ti,bit-shift = <4>;
0135 reg = <0x0204>;
0136 };
0137
0138 mcbsp5_ick: mcbsp5_ick@214 {
0139 #clock-cells = <0>;
0140 compatible = "ti,omap3-interface-clock";
0141 clocks = <&l4_ck>;
0142 ti,bit-shift = <5>;
0143 reg = <0x0214>;
0144 };
0145
0146 mcbsp5_gate_fck: mcbsp5_gate_fck@204 {
0147 #clock-cells = <0>;
0148 compatible = "ti,composite-gate-clock";
0149 clocks = <&mcbsp_clks>;
0150 ti,bit-shift = <5>;
0151 reg = <0x0204>;
0152 };
0153
0154 mcspi3_ick: mcspi3_ick@214 {
0155 #clock-cells = <0>;
0156 compatible = "ti,omap3-interface-clock";
0157 clocks = <&l4_ck>;
0158 ti,bit-shift = <9>;
0159 reg = <0x0214>;
0160 };
0161
0162 mcspi3_fck: mcspi3_fck@204 {
0163 #clock-cells = <0>;
0164 compatible = "ti,wait-gate-clock";
0165 clocks = <&func_48m_ck>;
0166 ti,bit-shift = <9>;
0167 reg = <0x0204>;
0168 };
0169
0170 icr_ick: icr_ick@410 {
0171 #clock-cells = <0>;
0172 compatible = "ti,omap3-interface-clock";
0173 clocks = <&sys_ck>;
0174 ti,bit-shift = <6>;
0175 reg = <0x0410>;
0176 };
0177
0178 i2chs1_fck: i2chs1_fck@204 {
0179 #clock-cells = <0>;
0180 compatible = "ti,omap2430-interface-clock";
0181 clocks = <&func_96m_ck>;
0182 ti,bit-shift = <19>;
0183 reg = <0x0204>;
0184 };
0185
0186 i2chs2_fck: i2chs2_fck@204 {
0187 #clock-cells = <0>;
0188 compatible = "ti,omap2430-interface-clock";
0189 clocks = <&func_96m_ck>;
0190 ti,bit-shift = <20>;
0191 reg = <0x0204>;
0192 };
0193
0194 usbhs_ick: usbhs_ick@214 {
0195 #clock-cells = <0>;
0196 compatible = "ti,omap3-interface-clock";
0197 clocks = <&core_l3_ck>;
0198 ti,bit-shift = <6>;
0199 reg = <0x0214>;
0200 };
0201
0202 mmchs1_ick: mmchs1_ick@214 {
0203 #clock-cells = <0>;
0204 compatible = "ti,omap3-interface-clock";
0205 clocks = <&l4_ck>;
0206 ti,bit-shift = <7>;
0207 reg = <0x0214>;
0208 };
0209
0210 mmchs1_fck: mmchs1_fck@204 {
0211 #clock-cells = <0>;
0212 compatible = "ti,wait-gate-clock";
0213 clocks = <&func_96m_ck>;
0214 ti,bit-shift = <7>;
0215 reg = <0x0204>;
0216 };
0217
0218 mmchs2_ick: mmchs2_ick@214 {
0219 #clock-cells = <0>;
0220 compatible = "ti,omap3-interface-clock";
0221 clocks = <&l4_ck>;
0222 ti,bit-shift = <8>;
0223 reg = <0x0214>;
0224 };
0225
0226 mmchs2_fck: mmchs2_fck@204 {
0227 #clock-cells = <0>;
0228 compatible = "ti,wait-gate-clock";
0229 clocks = <&func_96m_ck>;
0230 ti,bit-shift = <8>;
0231 reg = <0x0204>;
0232 };
0233
0234 gpio5_ick: gpio5_ick@214 {
0235 #clock-cells = <0>;
0236 compatible = "ti,omap3-interface-clock";
0237 clocks = <&l4_ck>;
0238 ti,bit-shift = <10>;
0239 reg = <0x0214>;
0240 };
0241
0242 gpio5_fck: gpio5_fck@204 {
0243 #clock-cells = <0>;
0244 compatible = "ti,wait-gate-clock";
0245 clocks = <&func_32k_ck>;
0246 ti,bit-shift = <10>;
0247 reg = <0x0204>;
0248 };
0249
0250 mdm_intc_ick: mdm_intc_ick@214 {
0251 #clock-cells = <0>;
0252 compatible = "ti,omap3-interface-clock";
0253 clocks = <&l4_ck>;
0254 ti,bit-shift = <11>;
0255 reg = <0x0214>;
0256 };
0257
0258 mmchsdb1_fck: mmchsdb1_fck@204 {
0259 #clock-cells = <0>;
0260 compatible = "ti,wait-gate-clock";
0261 clocks = <&func_32k_ck>;
0262 ti,bit-shift = <16>;
0263 reg = <0x0204>;
0264 };
0265
0266 mmchsdb2_fck: mmchsdb2_fck@204 {
0267 #clock-cells = <0>;
0268 compatible = "ti,wait-gate-clock";
0269 clocks = <&func_32k_ck>;
0270 ti,bit-shift = <17>;
0271 reg = <0x0204>;
0272 };
0273 };
0274
0275 &prcm_clockdomains {
0276 gfx_clkdm: gfx_clkdm {
0277 compatible = "ti,clockdomain";
0278 clocks = <&gfx_ick>;
0279 };
0280
0281 core_l3_clkdm: core_l3_clkdm {
0282 compatible = "ti,clockdomain";
0283 clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>;
0284 };
0285
0286 wkup_clkdm: wkup_clkdm {
0287 compatible = "ti,clockdomain";
0288 clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
0289 <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
0290 <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>,
0291 <&icr_ick>;
0292 };
0293
0294 dss_clkdm: dss_clkdm {
0295 compatible = "ti,clockdomain";
0296 clocks = <&dss_ick>, <&dss_54m_fck>;
0297 };
0298
0299 core_l4_clkdm: core_l4_clkdm {
0300 compatible = "ti,clockdomain";
0301 clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
0302 <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
0303 <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
0304 <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
0305 <&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>,
0306 <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
0307 <&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>,
0308 <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>,
0309 <&uart3_fck>, <&cam_ick>, <&mailboxes_ick>,
0310 <&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>,
0311 <&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>,
0312 <&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>,
0313 <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
0314 <&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>,
0315 <&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>,
0316 <&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>,
0317 <&mmchsdb2_fck>;
0318 };
0319
0320 mdm_clkdm: mdm_clkdm {
0321 compatible = "ti,clockdomain";
0322 clocks = <&mdm_osc_ck>;
0323 };
0324 };
0325
0326 &func_96m_ck {
0327 compatible = "ti,mux-clock";
0328 clocks = <&apll96_ck>, <&alt_ck>;
0329 ti,bit-shift = <4>;
0330 reg = <0x0540>;
0331 };
0332
0333 &dsp_div_fck {
0334 ti,max-div = <4>;
0335 ti,index-starts-at-one;
0336 };
0337
0338 &ssi_ssr_sst_div_fck {
0339 ti,max-div = <5>;
0340 ti,index-starts-at-one;
0341 };
