0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for OMAP2420 clock data
0004 *
0005 * Copyright (C) 2014 Texas Instruments, Inc.
0006 */
0007
0008 &prcm_clocks {
0009 sys_clkout2_src_gate: sys_clkout2_src_gate@70 {
0010 #clock-cells = <0>;
0011 compatible = "ti,composite-no-wait-gate-clock";
0012 clocks = <&core_ck>;
0013 ti,bit-shift = <15>;
0014 reg = <0x0070>;
0015 };
0016
0017 sys_clkout2_src_mux: sys_clkout2_src_mux@70 {
0018 #clock-cells = <0>;
0019 compatible = "ti,composite-mux-clock";
0020 clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
0021 ti,bit-shift = <8>;
0022 reg = <0x0070>;
0023 };
0024
0025 sys_clkout2_src: sys_clkout2_src {
0026 #clock-cells = <0>;
0027 compatible = "ti,composite-clock";
0028 clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
0029 };
0030
0031 sys_clkout2: sys_clkout2@70 {
0032 #clock-cells = <0>;
0033 compatible = "ti,divider-clock";
0034 clocks = <&sys_clkout2_src>;
0035 ti,bit-shift = <11>;
0036 ti,max-div = <64>;
0037 reg = <0x0070>;
0038 ti,index-power-of-two;
0039 };
0040
0041 dsp_gate_ick: dsp_gate_ick@810 {
0042 #clock-cells = <0>;
0043 compatible = "ti,composite-interface-clock";
0044 clocks = <&dsp_fck>;
0045 ti,bit-shift = <1>;
0046 reg = <0x0810>;
0047 };
0048
0049 dsp_div_ick: dsp_div_ick@840 {
0050 #clock-cells = <0>;
0051 compatible = "ti,composite-divider-clock";
0052 clocks = <&dsp_fck>;
0053 ti,bit-shift = <5>;
0054 ti,max-div = <3>;
0055 reg = <0x0840>;
0056 ti,index-starts-at-one;
0057 };
0058
0059 dsp_ick: dsp_ick {
0060 #clock-cells = <0>;
0061 compatible = "ti,composite-clock";
0062 clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
0063 };
0064
0065 iva1_gate_ifck: iva1_gate_ifck@800 {
0066 #clock-cells = <0>;
0067 compatible = "ti,composite-gate-clock";
0068 clocks = <&core_ck>;
0069 ti,bit-shift = <10>;
0070 reg = <0x0800>;
0071 };
0072
0073 iva1_div_ifck: iva1_div_ifck@840 {
0074 #clock-cells = <0>;
0075 compatible = "ti,composite-divider-clock";
0076 clocks = <&core_ck>;
0077 ti,bit-shift = <8>;
0078 reg = <0x0840>;
0079 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
0080 };
0081
0082 iva1_ifck: iva1_ifck {
0083 #clock-cells = <0>;
0084 compatible = "ti,composite-clock";
0085 clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
0086 };
0087
0088 iva1_ifck_div: iva1_ifck_div {
0089 #clock-cells = <0>;
0090 compatible = "fixed-factor-clock";
0091 clocks = <&iva1_ifck>;
0092 clock-mult = <1>;
0093 clock-div = <2>;
0094 };
0095
0096 iva1_mpu_int_ifck: iva1_mpu_int_ifck@800 {
0097 #clock-cells = <0>;
0098 compatible = "ti,wait-gate-clock";
0099 clocks = <&iva1_ifck_div>;
0100 ti,bit-shift = <8>;
0101 reg = <0x0800>;
0102 };
0103
0104 wdt3_ick: wdt3_ick@210 {
0105 #clock-cells = <0>;
0106 compatible = "ti,omap3-interface-clock";
0107 clocks = <&l4_ck>;
0108 ti,bit-shift = <28>;
0109 reg = <0x0210>;
0110 };
0111
0112 wdt3_fck: wdt3_fck@200 {
0113 #clock-cells = <0>;
0114 compatible = "ti,wait-gate-clock";
0115 clocks = <&func_32k_ck>;
0116 ti,bit-shift = <28>;
0117 reg = <0x0200>;
0118 };
0119
0120 mmc_ick: mmc_ick@210 {
0121 #clock-cells = <0>;
0122 compatible = "ti,omap3-interface-clock";
0123 clocks = <&l4_ck>;
0124 ti,bit-shift = <26>;
0125 reg = <0x0210>;
0126 };
0127
0128 mmc_fck: mmc_fck@200 {
0129 #clock-cells = <0>;
0130 compatible = "ti,wait-gate-clock";
0131 clocks = <&func_96m_ck>;
0132 ti,bit-shift = <26>;
0133 reg = <0x0200>;
0134 };
0135
0136 eac_ick: eac_ick@210 {
0137 #clock-cells = <0>;
0138 compatible = "ti,omap3-interface-clock";
0139 clocks = <&l4_ck>;
0140 ti,bit-shift = <24>;
0141 reg = <0x0210>;
0142 };
0143
0144 eac_fck: eac_fck@200 {
0145 #clock-cells = <0>;
0146 compatible = "ti,wait-gate-clock";
0147 clocks = <&func_96m_ck>;
0148 ti,bit-shift = <24>;
0149 reg = <0x0200>;
0150 };
0151
0152 i2c1_fck: i2c1_fck@200 {
0153 #clock-cells = <0>;
0154 compatible = "ti,wait-gate-clock";
0155 clocks = <&func_12m_ck>;
0156 ti,bit-shift = <19>;
0157 reg = <0x0200>;
0158 };
0159
0160 i2c2_fck: i2c2_fck@200 {
0161 #clock-cells = <0>;
0162 compatible = "ti,wait-gate-clock";
0163 clocks = <&func_12m_ck>;
0164 ti,bit-shift = <20>;
0165 reg = <0x0200>;
0166 };
0167
0168 vlynq_ick: vlynq_ick@210 {
0169 #clock-cells = <0>;
0170 compatible = "ti,omap3-interface-clock";
0171 clocks = <&core_l3_ck>;
0172 ti,bit-shift = <3>;
0173 reg = <0x0210>;
0174 };
0175
0176 vlynq_gate_fck: vlynq_gate_fck@200 {
0177 #clock-cells = <0>;
0178 compatible = "ti,composite-gate-clock";
0179 clocks = <&core_ck>;
0180 ti,bit-shift = <3>;
0181 reg = <0x0200>;
0182 };
0183
0184 core_d18_ck: core_d18_ck {
0185 #clock-cells = <0>;
0186 compatible = "fixed-factor-clock";
0187 clocks = <&core_ck>;
0188 clock-mult = <1>;
0189 clock-div = <18>;
0190 };
0191
0192 vlynq_mux_fck: vlynq_mux_fck@240 {
0193 #clock-cells = <0>;
0194 compatible = "ti,composite-mux-clock";
0195 clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>;
0196 ti,bit-shift = <15>;
0197 reg = <0x0240>;
0198 };
0199
0200 vlynq_fck: vlynq_fck {
0201 #clock-cells = <0>;
0202 compatible = "ti,composite-clock";
0203 clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>;
0204 };
0205 };
0206
0207 &prcm_clockdomains {
0208 gfx_clkdm: gfx_clkdm {
0209 compatible = "ti,clockdomain";
0210 clocks = <&gfx_ick>;
0211 };
0212
0213 core_l3_clkdm: core_l3_clkdm {
0214 compatible = "ti,clockdomain";
0215 clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>;
0216 };
0217
0218 wkup_clkdm: wkup_clkdm {
0219 compatible = "ti,clockdomain";
0220 clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
0221 <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
0222 <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>;
0223 };
0224
0225 iva1_clkdm: iva1_clkdm {
0226 compatible = "ti,clockdomain";
0227 clocks = <&iva1_mpu_int_ifck>;
0228 };
0229
0230 dss_clkdm: dss_clkdm {
0231 compatible = "ti,clockdomain";
0232 clocks = <&dss_ick>, <&dss_54m_fck>;
0233 };
0234
0235 core_l4_clkdm: core_l4_clkdm {
0236 compatible = "ti,clockdomain";
0237 clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
0238 <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
0239 <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
0240 <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>,
0241 <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
0242 <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>,
0243 <&uart3_ick>, <&uart3_fck>, <&cam_ick>,
0244 <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>,
0245 <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>,
0246 <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>,
0247 <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>,
0248 <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>,
0249 <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
0250 <&pka_ick>;
0251 };
0252 };
0253
0254 &func_96m_ck {
0255 compatible = "fixed-factor-clock";
0256 clocks = <&apll96_ck>;
0257 clock-mult = <1>;
0258 clock-div = <1>;
0259 };
0260
0261 &dsp_div_fck {
0262 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
0263 };
0264
0265 &ssi_ssr_sst_div_fck {
0266 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
0267 };
