0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for OMAP2 SoC
0004 *
0005 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 #include <dt-bindings/bus/ti-sysc.h>
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/interrupt-controller/irq.h>
0011 #include <dt-bindings/pinctrl/omap.h>
0012
0013 / {
0014 compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
0015 interrupt-parent = <&intc>;
0016 #address-cells = <1>;
0017 #size-cells = <1>;
0018 chosen { };
0019
0020 aliases {
0021 serial0 = &uart1;
0022 serial1 = &uart2;
0023 serial2 = &uart3;
0024 i2c0 = &i2c1;
0025 i2c1 = &i2c2;
0026 };
0027
0028 cpus {
0029 #address-cells = <0>;
0030 #size-cells = <0>;
0031
0032 cpu {
0033 compatible = "arm,arm1136jf-s";
0034 device_type = "cpu";
0035 };
0036 };
0037
0038 pmu {
0039 compatible = "arm,arm1136-pmu";
0040 interrupts = <3>;
0041 };
0042
0043 soc {
0044 compatible = "ti,omap-infra";
0045 mpu {
0046 compatible = "ti,omap2-mpu";
0047 ti,hwmods = "mpu";
0048 };
0049 };
0050
0051 ocp {
0052 compatible = "simple-bus";
0053 #address-cells = <1>;
0054 #size-cells = <1>;
0055 ranges;
0056 ti,hwmods = "l3_main";
0057
0058 aes: aes@480a6000 {
0059 compatible = "ti,omap2-aes";
0060 ti,hwmods = "aes";
0061 reg = <0x480a6000 0x50>;
0062 dmas = <&sdma 9 &sdma 10>;
0063 dma-names = "tx", "rx";
0064 };
0065
0066 hdq1w: 1w@480b2000 {
0067 compatible = "ti,omap2420-1w";
0068 ti,hwmods = "hdq1w";
0069 reg = <0x480b2000 0x1000>;
0070 interrupts = <58>;
0071 };
0072
0073 intc: interrupt-controller@1 {
0074 compatible = "ti,omap2-intc";
0075 interrupt-controller;
0076 #interrupt-cells = <1>;
0077 reg = <0x480FE000 0x1000>;
0078 };
0079
0080 target-module@48056000 {
0081 compatible = "ti,sysc-omap2", "ti,sysc";
0082 reg = <0x48056000 0x4>,
0083 <0x4805602c 0x4>,
0084 <0x48056028 0x4>;
0085 reg-names = "rev", "sysc", "syss";
0086 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0087 SYSC_OMAP2_EMUFREE |
0088 SYSC_OMAP2_SOFTRESET |
0089 SYSC_OMAP2_AUTOIDLE)>;
0090 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0091 <SYSC_IDLE_NO>,
0092 <SYSC_IDLE_SMART>;
0093 ti,syss-mask = <1>;
0094 clocks = <&core_l3_ck>;
0095 clock-names = "fck";
0096 #address-cells = <1>;
0097 #size-cells = <1>;
0098 ranges = <0 0x48056000 0x1000>;
0099
0100 sdma: dma-controller@0 {
0101 compatible = "ti,omap2420-sdma", "ti,omap-sdma";
0102 reg = <0 0x1000>;
0103 interrupts = <12>,
0104 <13>,
0105 <14>,
0106 <15>;
0107 #dma-cells = <1>;
0108 dma-channels = <32>;
0109 dma-requests = <64>;
0110 };
0111 };
0112
0113 i2c1: i2c@48070000 {
0114 compatible = "ti,omap2-i2c";
0115 ti,hwmods = "i2c1";
0116 reg = <0x48070000 0x80>;
0117 #address-cells = <1>;
0118 #size-cells = <0>;
0119 interrupts = <56>;
0120 };
0121
0122 i2c2: i2c@48072000 {
0123 compatible = "ti,omap2-i2c";
0124 ti,hwmods = "i2c2";
0125 reg = <0x48072000 0x80>;
0126 #address-cells = <1>;
0127 #size-cells = <0>;
0128 interrupts = <57>;
0129 };
0130
0131 mcspi1: spi@48098000 {
0132 compatible = "ti,omap2-mcspi";
0133 ti,hwmods = "mcspi1";
0134 reg = <0x48098000 0x100>;
0135 interrupts = <65>;
0136 dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38
0137 &sdma 39 &sdma 40 &sdma 41 &sdma 42>;
0138 dma-names = "tx0", "rx0", "tx1", "rx1",
0139 "tx2", "rx2", "tx3", "rx3";
0140 };
0141
0142 mcspi2: spi@4809a000 {
0143 compatible = "ti,omap2-mcspi";
0144 ti,hwmods = "mcspi2";
0145 reg = <0x4809a000 0x100>;
0146 interrupts = <66>;
0147 dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>;
0148 dma-names = "tx0", "rx0", "tx1", "rx1";
0149 };
0150
0151 rng: rng@480a0000 {
0152 compatible = "ti,omap2-rng";
0153 ti,hwmods = "rng";
0154 reg = <0x480a0000 0x50>;
0155 interrupts = <52>;
0156 };
0157
0158 sham: sham@480a4000 {
0159 compatible = "ti,omap2-sham";
0160 ti,hwmods = "sham";
0161 reg = <0x480a4000 0x64>;
0162 interrupts = <51>;
0163 dmas = <&sdma 13>;
0164 dma-names = "rx";
0165 };
0166
0167 uart1: serial@4806a000 {
0168 compatible = "ti,omap2-uart";
0169 ti,hwmods = "uart1";
0170 reg = <0x4806a000 0x2000>;
0171 interrupts = <72>;
0172 dmas = <&sdma 49 &sdma 50>;
0173 dma-names = "tx", "rx";
0174 clock-frequency = <48000000>;
0175 };
0176
0177 uart2: serial@4806c000 {
0178 compatible = "ti,omap2-uart";
0179 ti,hwmods = "uart2";
0180 reg = <0x4806c000 0x400>;
0181 interrupts = <73>;
0182 dmas = <&sdma 51 &sdma 52>;
0183 dma-names = "tx", "rx";
0184 clock-frequency = <48000000>;
0185 };
0186
0187 uart3: serial@4806e000 {
0188 compatible = "ti,omap2-uart";
0189 ti,hwmods = "uart3";
0190 reg = <0x4806e000 0x400>;
0191 interrupts = <74>;
0192 dmas = <&sdma 53 &sdma 54>;
0193 dma-names = "tx", "rx";
0194 clock-frequency = <48000000>;
0195 };
0196
0197 timer2_target: target-module@4802a000 {
0198 compatible = "ti,sysc-omap2-timer", "ti,sysc";
0199 reg = <0x4802a000 0x4>,
0200 <0x4802a010 0x4>,
0201 <0x4802a014 0x4>;
0202 reg-names = "rev", "sysc", "syss";
0203 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0204 SYSC_OMAP2_EMUFREE |
0205 SYSC_OMAP2_ENAWAKEUP |
0206 SYSC_OMAP2_SOFTRESET |
0207 SYSC_OMAP2_AUTOIDLE)>;
0208 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0209 <SYSC_IDLE_NO>,
0210 <SYSC_IDLE_SMART>;
0211 ti,syss-mask = <1>;
0212 clocks = <&gpt2_fck>, <&gpt2_ick>;
0213 clock-names = "fck", "ick";
0214 #address-cells = <1>;
0215 #size-cells = <1>;
0216 ranges = <0x0 0x4802a000 0x1000>;
0217
0218 timer2: timer@0 {
0219 compatible = "ti,omap2420-timer";
0220 reg = <0 0x400>;
0221 interrupts = <38>;
0222 };
0223 };
0224
0225 timer3: timer@48078000 {
0226 compatible = "ti,omap2420-timer";
0227 reg = <0x48078000 0x400>;
0228 interrupts = <39>;
0229 ti,hwmods = "timer3";
0230 };
0231
0232 timer4: timer@4807a000 {
0233 compatible = "ti,omap2420-timer";
0234 reg = <0x4807a000 0x400>;
0235 interrupts = <40>;
0236 ti,hwmods = "timer4";
0237 };
0238
0239 timer5: timer@4807c000 {
0240 compatible = "ti,omap2420-timer";
0241 reg = <0x4807c000 0x400>;
0242 interrupts = <41>;
0243 ti,hwmods = "timer5";
0244 ti,timer-dsp;
0245 };
0246
0247 timer6: timer@4807e000 {
0248 compatible = "ti,omap2420-timer";
0249 reg = <0x4807e000 0x400>;
0250 interrupts = <42>;
0251 ti,hwmods = "timer6";
0252 ti,timer-dsp;
0253 };
0254
0255 timer7: timer@48080000 {
0256 compatible = "ti,omap2420-timer";
0257 reg = <0x48080000 0x400>;
0258 interrupts = <43>;
0259 ti,hwmods = "timer7";
0260 ti,timer-dsp;
0261 };
0262
0263 timer8: timer@48082000 {
0264 compatible = "ti,omap2420-timer";
0265 reg = <0x48082000 0x400>;
0266 interrupts = <44>;
0267 ti,hwmods = "timer8";
0268 ti,timer-dsp;
0269 };
0270
0271 timer9: timer@48084000 {
0272 compatible = "ti,omap2420-timer";
0273 reg = <0x48084000 0x400>;
0274 interrupts = <45>;
0275 ti,hwmods = "timer9";
0276 ti,timer-pwm;
0277 };
0278
0279 timer10: timer@48086000 {
0280 compatible = "ti,omap2420-timer";
0281 reg = <0x48086000 0x400>;
0282 interrupts = <46>;
0283 ti,hwmods = "timer10";
0284 ti,timer-pwm;
0285 };
0286
0287 timer11: timer@48088000 {
0288 compatible = "ti,omap2420-timer";
0289 reg = <0x48088000 0x400>;
0290 interrupts = <47>;
0291 ti,hwmods = "timer11";
0292 ti,timer-pwm;
0293 };
0294
0295 timer12: timer@4808a000 {
0296 compatible = "ti,omap2420-timer";
0297 reg = <0x4808a000 0x400>;
0298 interrupts = <48>;
0299 ti,hwmods = "timer12";
0300 ti,timer-pwm;
0301 };
0302
0303 dss: dss@48050000 {
0304 compatible = "ti,omap2-dss";
0305 reg = <0x48050000 0x400>;
0306 status = "disabled";
0307 ti,hwmods = "dss_core";
0308 #address-cells = <1>;
0309 #size-cells = <1>;
0310 ranges;
0311
0312 dispc@48050400 {
0313 compatible = "ti,omap2-dispc";
0314 reg = <0x48050400 0x400>;
0315 interrupts = <25>;
0316 ti,hwmods = "dss_dispc";
0317 };
0318
0319 rfbi: encoder@48050800 {
0320 compatible = "ti,omap2-rfbi";
0321 reg = <0x48050800 0x400>;
0322 status = "disabled";
0323 ti,hwmods = "dss_rfbi";
0324 };
0325
0326 venc: encoder@48050c00 {
0327 compatible = "ti,omap2-venc";
0328 reg = <0x48050c00 0x400>;
0329 status = "disabled";
0330 ti,hwmods = "dss_venc";
0331 };
0332 };
0333 };
0334 };
