0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
0003 // Copyright 2018 Google, Inc.
0004
0005 #include "nuvoton-common-npcm7xx.dtsi"
0006
0007 / {
0008 #address-cells = <1>;
0009 #size-cells = <1>;
0010 interrupt-parent = <&gic>;
0011
0012 cpus {
0013 #address-cells = <1>;
0014 #size-cells = <0>;
0015 enable-method = "nuvoton,npcm750-smp";
0016
0017 cpu@0 {
0018 device_type = "cpu";
0019 compatible = "arm,cortex-a9";
0020 clocks = <&clk NPCM7XX_CLK_CPU>;
0021 clock-names = "clk_cpu";
0022 reg = <0>;
0023 next-level-cache = <&l2>;
0024 };
0025
0026 cpu@1 {
0027 device_type = "cpu";
0028 compatible = "arm,cortex-a9";
0029 clocks = <&clk NPCM7XX_CLK_CPU>;
0030 clock-names = "clk_cpu";
0031 reg = <1>;
0032 next-level-cache = <&l2>;
0033 };
0034 };
0035
0036 soc {
0037 timer@3fe600 {
0038 compatible = "arm,cortex-a9-twd-timer";
0039 reg = <0x3fe600 0x20>;
0040 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
0041 IRQ_TYPE_LEVEL_HIGH)>;
0042 clocks = <&clk NPCM7XX_CLK_AHB>;
0043 };
0044 };
0045
0046 ahb {
0047 gmac1: eth@f0804000 {
0048 device_type = "network";
0049 compatible = "snps,dwmac";
0050 reg = <0xf0804000 0x2000>;
0051 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0052 interrupt-names = "macirq";
0053 ethernet = <1>;
0054 clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>;
0055 clock-names = "stmmaceth", "clk_gmac";
0056 pinctrl-names = "default";
0057 pinctrl-0 = <&rg2_pins
0058 &rg2mdio_pins>;
0059 status = "disabled";
0060 };
0061 };
0062 };
