0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
0003 // Copyright 2018 Google, Inc.
0004
0005 /dts-v1/;
0006 #include "nuvoton-npcm750.dtsi"
0007 #include "dt-bindings/gpio/gpio.h"
0008 #include "nuvoton-npcm750-pincfg-evb.dtsi"
0009
0010 / {
0011 model = "Nuvoton npcm750 Development Board (Device Tree)";
0012 compatible = "nuvoton,npcm750-evb", "nuvoton,npcm750";
0013
0014 aliases {
0015 ethernet2 = &gmac0;
0016 ethernet3 = &gmac1;
0017 serial0 = &serial0;
0018 serial1 = &serial1;
0019 serial2 = &serial2;
0020 serial3 = &serial3;
0021 i2c0 = &i2c0;
0022 i2c1 = &i2c1;
0023 i2c2 = &i2c2;
0024 i2c3 = &i2c3;
0025 i2c4 = &i2c4;
0026 i2c5 = &i2c5;
0027 i2c6 = &i2c6;
0028 i2c7 = &i2c7;
0029 i2c8 = &i2c8;
0030 i2c9 = &i2c9;
0031 i2c10 = &i2c10;
0032 i2c11 = &i2c11;
0033 i2c12 = &i2c12;
0034 i2c13 = &i2c13;
0035 i2c14 = &i2c14;
0036 i2c15 = &i2c15;
0037 spi0 = &spi0;
0038 spi1 = &spi1;
0039 fiu0 = &fiu0;
0040 fiu1 = &fiu3;
0041 fiu2 = &fiux;
0042 };
0043
0044 chosen {
0045 stdout-path = &serial3;
0046 };
0047
0048 memory {
0049 device_type = "memory";
0050 reg = <0x0 0x20000000>;
0051 };
0052 };
0053
0054 &gmac0 {
0055 phy-mode = "rgmii-id";
0056 status = "okay";
0057 };
0058
0059 &gmac1 {
0060 phy-mode = "rgmii-id";
0061 status = "okay";
0062 };
0063
0064 &ehci1 {
0065 status = "okay";
0066 };
0067
0068 &fiu0 {
0069 status = "okay";
0070 flash@0 {
0071 compatible = "jedec,spi-nor";
0072 #address-cells = <1>;
0073 #size-cells = <1>;
0074 spi-rx-bus-width = <2>;
0075 reg = <0>;
0076 spi-max-frequency = <5000000>;
0077 partitions@80000000 {
0078 compatible = "fixed-partitions";
0079 #address-cells = <1>;
0080 #size-cells = <1>;
0081 bbuboot1@0 {
0082 label = "bb-uboot-1";
0083 reg = <0x0000000 0x80000>;
0084 read-only;
0085 };
0086 bbuboot2@80000 {
0087 label = "bb-uboot-2";
0088 reg = <0x0080000 0x80000>;
0089 read-only;
0090 };
0091 envparam@100000 {
0092 label = "env-param";
0093 reg = <0x0100000 0x40000>;
0094 read-only;
0095 };
0096 spare@140000 {
0097 label = "spare";
0098 reg = <0x0140000 0xC0000>;
0099 };
0100 kernel@200000 {
0101 label = "kernel";
0102 reg = <0x0200000 0x400000>;
0103 };
0104 rootfs@600000 {
0105 label = "rootfs";
0106 reg = <0x0600000 0x700000>;
0107 };
0108 spare1@d00000 {
0109 label = "spare1";
0110 reg = <0x0D00000 0x200000>;
0111 };
0112 spare2@f00000 {
0113 label = "spare2";
0114 reg = <0x0F00000 0x200000>;
0115 };
0116 spare3@1100000 {
0117 label = "spare3";
0118 reg = <0x1100000 0x200000>;
0119 };
0120 spare4@1300000 {
0121 label = "spare4";
0122 reg = <0x1300000 0x0>;
0123 };
0124 };
0125 };
0126 };
0127
0128 &fiu3 {
0129 pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
0130 status = "okay";
0131 flash@0 {
0132 compatible = "jedec,spi-nor";
0133 #address-cells = <1>;
0134 #size-cells = <1>;
0135 spi-rx-bus-width = <2>;
0136 reg = <0>;
0137 spi-max-frequency = <5000000>;
0138 partitions@A0000000 {
0139 compatible = "fixed-partitions";
0140 #address-cells = <1>;
0141 #size-cells = <1>;
0142 system1@0 {
0143 label = "spi3-system1";
0144 reg = <0x0 0x0>;
0145 };
0146 };
0147 };
0148 };
0149
0150 &fiux {
0151 spix-mode;
0152 };
0153
0154 &watchdog1 {
0155 status = "okay";
0156 };
0157
0158 &rng {
0159 status = "okay";
0160 };
0161
0162 &serial0 {
0163 status = "okay";
0164 };
0165
0166 &serial1 {
0167 status = "okay";
0168 };
0169
0170 &serial2 {
0171 status = "okay";
0172 };
0173
0174 &serial3 {
0175 status = "okay";
0176 };
0177
0178 &adc {
0179 status = "okay";
0180 };
0181
0182 &lpc_kcs {
0183 kcs1: kcs1@0 {
0184 status = "okay";
0185 };
0186
0187 kcs2: kcs2@0 {
0188 status = "okay";
0189 };
0190
0191 kcs3: kcs3@0 {
0192 status = "okay";
0193 };
0194 };
0195
0196 /* lm75 on SVB */
0197 &i2c0 {
0198 clock-frequency = <100000>;
0199 status = "okay";
0200 lm75@48 {
0201 compatible = "lm75";
0202 reg = <0x48>;
0203 status = "okay";
0204 };
0205 };
0206
0207 /* lm75 on EB */
0208 &i2c1 {
0209 clock-frequency = <100000>;
0210 status = "okay";
0211 lm75@48 {
0212 compatible = "lm75";
0213 reg = <0x48>;
0214 status = "okay";
0215 };
0216 };
0217
0218 /* tmp100 on EB */
0219 &i2c2 {
0220 clock-frequency = <100000>;
0221 status = "okay";
0222 tmp100@48 {
0223 compatible = "tmp100";
0224 reg = <0x48>;
0225 status = "okay";
0226 };
0227 };
0228
0229 &i2c3 {
0230 clock-frequency = <100000>;
0231 status = "okay";
0232 };
0233
0234 &i2c5 {
0235 clock-frequency = <100000>;
0236 status = "okay";
0237 };
0238
0239 /* tmp100 on SVB */
0240 &i2c6 {
0241 clock-frequency = <100000>;
0242 status = "okay";
0243 tmp100@48 {
0244 compatible = "tmp100";
0245 reg = <0x48>;
0246 status = "okay";
0247 };
0248 };
0249
0250 &i2c7 {
0251 clock-frequency = <100000>;
0252 status = "okay";
0253 };
0254
0255 &i2c8 {
0256 clock-frequency = <100000>;
0257 status = "okay";
0258 };
0259
0260 &i2c9 {
0261 clock-frequency = <100000>;
0262 status = "okay";
0263 };
0264
0265 &i2c10 {
0266 clock-frequency = <100000>;
0267 status = "okay";
0268 };
0269
0270 &i2c11 {
0271 clock-frequency = <100000>;
0272 status = "okay";
0273 };
0274
0275 &i2c14 {
0276 clock-frequency = <100000>;
0277 status = "okay";
0278 };
0279
0280 &pwm_fan {
0281 status = "okay";
0282 fan@0 {
0283 reg = <0x00>;
0284 fan-tach-ch = /bits/ 8 <0x00 0x01>;
0285 cooling-levels = <127 255>;
0286 };
0287 fan@1 {
0288 reg = <0x01>;
0289 fan-tach-ch = /bits/ 8 <0x02 0x03>;
0290 cooling-levels = /bits/ 8 <127 255>;
0291 };
0292 fan@2 {
0293 reg = <0x02>;
0294 fan-tach-ch = /bits/ 8 <0x04 0x05>;
0295 cooling-levels = /bits/ 8 <127 255>;
0296 };
0297 fan@3 {
0298 reg = <0x03>;
0299 fan-tach-ch = /bits/ 8 <0x06 0x07>;
0300 cooling-levels = /bits/ 8 <127 255>;
0301 };
0302 fan@4 {
0303 reg = <0x04>;
0304 fan-tach-ch = /bits/ 8 <0x08 0x09>;
0305 cooling-levels = /bits/ 8 <127 255>;
0306 };
0307 fan@5 {
0308 reg = <0x05>;
0309 fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
0310 cooling-levels = /bits/ 8 <127 255>;
0311 };
0312 fan@6 {
0313 reg = <0x06>;
0314 fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
0315 cooling-levels = /bits/ 8 <127 255>;
0316 };
0317 fan@7 {
0318 reg = <0x07>;
0319 fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
0320 cooling-levels = /bits/ 8 <127 255>;
0321 };
0322 };
0323
0324 &spi0 {
0325 cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
0326 status = "okay";
0327 flash@0 {
0328 compatible = "winbond,w25q128",
0329 "jedec,spi-nor";
0330 reg = <0x0>;
0331 #address-cells = <1>;
0332 #size-cells = <1>;
0333 spi-max-frequency = <5000000>;
0334 partition@0 {
0335 label = "spi0_spare1";
0336 reg = <0x0000000 0x800000>;
0337 };
0338 partition@1 {
0339 label = "spi0_spare2";
0340 reg = <0x800000 0x0>;
0341 };
0342 };
0343 };
0344
0345 &spi1 {
0346 cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
0347 status = "okay";
0348 flash@0 {
0349 compatible = "winbond,w25q128fw",
0350 "jedec,spi-nor";
0351 reg = <0x0>;
0352 #address-cells = <1>;
0353 #size-cells = <1>;
0354 spi-max-frequency = <5000000>;
0355 partition@0 {
0356 label = "spi1_spare1";
0357 reg = <0x0000000 0x800000>;
0358 };
0359 partition@1 {
0360 label = "spi1_spare2";
0361 reg = <0x800000 0x0>;
0362 };
0363 };
0364 };
0365
0366 &pinctrl {
0367 pinctrl-names = "default";
0368 pinctrl-0 = < &iox1_pins
0369 &pin8_input
0370 &pin9_output_high
0371 &pin10_input
0372 &pin11_output_high
0373 &pin16_input
0374 &pin24_output_high
0375 &pin25_output_low
0376 &pin32_output_high
0377 &jtag2_pins
0378 &pin61_output_high
0379 &pin62_output_high
0380 &pin63_output_high
0381 &lpc_pins
0382 &pin160_input
0383 &pin162_input
0384 &pin168_input
0385 &pin169_input
0386 &pin170_input
0387 &pin187_output_high
0388 &pin190_input
0389 &pin191_output_high
0390 &pin192_output_high
0391 &pin197_output_low
0392 &ddc_pins
0393 &pin218_input
0394 &pin219_output_low
0395 &pin220_output_low
0396 &pin221_output_high
0397 &pin222_input
0398 &pin223_output_low
0399 &spix_pins
0400 &pin228_output_low
0401 &pin231_output_high
0402 &pin255_input>;
0403 };
0404
