0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
0003 // Copyright 2018 Google, Inc.
0004
0005 #include <dt-bindings/interrupt-controller/arm-gic.h>
0006 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
0007 #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
0008
0009 / {
0010 #address-cells = <1>;
0011 #size-cells = <1>;
0012 interrupt-parent = <&gic>;
0013
0014 /* external reference clock */
0015 clk_refclk: clk_refclk {
0016 compatible = "fixed-clock";
0017 #clock-cells = <0>;
0018 clock-frequency = <25000000>;
0019 clock-output-names = "refclk";
0020 };
0021
0022 /* external reference clock for cpu. float in normal operation */
0023 clk_sysbypck: clk_sysbypck {
0024 compatible = "fixed-clock";
0025 #clock-cells = <0>;
0026 clock-frequency = <800000000>;
0027 clock-output-names = "sysbypck";
0028 };
0029
0030 /* external reference clock for MC. float in normal operation */
0031 clk_mcbypck: clk_mcbypck {
0032 compatible = "fixed-clock";
0033 #clock-cells = <0>;
0034 clock-frequency = <800000000>;
0035 clock-output-names = "mcbypck";
0036 };
0037
0038 /* external clock signal rg1refck, supplied by the phy */
0039 clk_rg1refck: clk_rg1refck {
0040 compatible = "fixed-clock";
0041 #clock-cells = <0>;
0042 clock-frequency = <125000000>;
0043 clock-output-names = "clk_rg1refck";
0044 };
0045
0046 /* external clock signal rg2refck, supplied by the phy */
0047 clk_rg2refck: clk_rg2refck {
0048 compatible = "fixed-clock";
0049 #clock-cells = <0>;
0050 clock-frequency = <125000000>;
0051 clock-output-names = "clk_rg2refck";
0052 };
0053
0054 clk_xin: clk_xin {
0055 compatible = "fixed-clock";
0056 #clock-cells = <0>;
0057 clock-frequency = <50000000>;
0058 clock-output-names = "clk_xin";
0059 };
0060
0061 soc {
0062 #address-cells = <1>;
0063 #size-cells = <1>;
0064 compatible = "simple-bus";
0065 interrupt-parent = <&gic>;
0066 ranges = <0x0 0xf0000000 0x00900000>;
0067
0068 scu: scu@3fe000 {
0069 compatible = "arm,cortex-a9-scu";
0070 reg = <0x3fe000 0x1000>;
0071 };
0072
0073 l2: cache-controller@3fc000 {
0074 compatible = "arm,pl310-cache";
0075 reg = <0x3fc000 0x1000>;
0076 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0077 cache-unified;
0078 cache-level = <2>;
0079 clocks = <&clk NPCM7XX_CLK_AXI>;
0080 arm,shared-override;
0081 };
0082
0083 gic: interrupt-controller@3ff000 {
0084 compatible = "arm,cortex-a9-gic";
0085 interrupt-controller;
0086 #interrupt-cells = <3>;
0087 reg = <0x3ff000 0x1000>,
0088 <0x3fe100 0x100>;
0089 };
0090
0091 gcr: gcr@800000 {
0092 compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd";
0093 reg = <0x800000 0x1000>;
0094 };
0095
0096 rst: rst@801000 {
0097 compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd";
0098 reg = <0x801000 0x6C>;
0099 };
0100 };
0101
0102 ahb {
0103 #address-cells = <1>;
0104 #size-cells = <1>;
0105 compatible = "simple-bus";
0106 interrupt-parent = <&gic>;
0107 ranges;
0108
0109 rstc: rstc@f0801000 {
0110 compatible = "nuvoton,npcm750-reset";
0111 reg = <0xf0801000 0x70>;
0112 #reset-cells = <2>;
0113 nuvoton,sysgcr = <&gcr>;
0114 };
0115
0116 clk: clock-controller@f0801000 {
0117 compatible = "nuvoton,npcm750-clk", "syscon";
0118 #clock-cells = <1>;
0119 clock-controller;
0120 reg = <0xf0801000 0x1000>;
0121 clock-names = "refclk", "sysbypck", "mcbypck";
0122 clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
0123 };
0124
0125 gmac0: eth@f0802000 {
0126 device_type = "network";
0127 compatible = "snps,dwmac";
0128 reg = <0xf0802000 0x2000>;
0129 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0130 interrupt-names = "macirq";
0131 ethernet = <0>;
0132 clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
0133 clock-names = "stmmaceth", "clk_gmac";
0134 pinctrl-names = "default";
0135 pinctrl-0 = <&rg1_pins
0136 &rg1mdio_pins>;
0137 status = "disabled";
0138 };
0139
0140 ehci1: usb@f0806000 {
0141 compatible = "nuvoton,npcm750-ehci";
0142 reg = <0xf0806000 0x1000>;
0143 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0144 status = "disabled";
0145 };
0146
0147 fiu0: spi@fb000000 {
0148 compatible = "nuvoton,npcm750-fiu";
0149 #address-cells = <1>;
0150 #size-cells = <0>;
0151 reg = <0xfb000000 0x1000>;
0152 reg-names = "control", "memory";
0153 clocks = <&clk NPCM7XX_CLK_SPI0>;
0154 clock-names = "clk_spi0";
0155 status = "disabled";
0156 };
0157
0158 fiu3: spi@c0000000 {
0159 compatible = "nuvoton,npcm750-fiu";
0160 #address-cells = <1>;
0161 #size-cells = <0>;
0162 reg = <0xc0000000 0x1000>;
0163 reg-names = "control", "memory";
0164 clocks = <&clk NPCM7XX_CLK_SPI3>;
0165 clock-names = "clk_spi3";
0166 pinctrl-names = "default";
0167 pinctrl-0 = <&spi3_pins>;
0168 status = "disabled";
0169 };
0170
0171 fiux: spi@fb001000 {
0172 compatible = "nuvoton,npcm750-fiu";
0173 #address-cells = <1>;
0174 #size-cells = <0>;
0175 reg = <0xfb001000 0x1000>;
0176 reg-names = "control", "memory";
0177 clocks = <&clk NPCM7XX_CLK_SPIX>;
0178 clock-names = "clk_spix";
0179 status = "disabled";
0180 };
0181
0182 apb {
0183 #address-cells = <1>;
0184 #size-cells = <1>;
0185 compatible = "simple-bus";
0186 interrupt-parent = <&gic>;
0187 ranges = <0x0 0xf0000000 0x00300000>;
0188
0189 lpc_kcs: lpc_kcs@7000 {
0190 compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon";
0191 reg = <0x7000 0x40>;
0192 reg-io-width = <1>;
0193
0194 #address-cells = <1>;
0195 #size-cells = <1>;
0196 ranges = <0x0 0x7000 0x40>;
0197
0198 kcs1: kcs1@0 {
0199 compatible = "nuvoton,npcm750-kcs-bmc";
0200 reg = <0x0 0x40>;
0201 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0202 kcs_chan = <1>;
0203 status = "disabled";
0204 };
0205
0206 kcs2: kcs2@0 {
0207 compatible = "nuvoton,npcm750-kcs-bmc";
0208 reg = <0x0 0x40>;
0209 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0210 kcs_chan = <2>;
0211 status = "disabled";
0212 };
0213
0214 kcs3: kcs3@0 {
0215 compatible = "nuvoton,npcm750-kcs-bmc";
0216 reg = <0x0 0x40>;
0217 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0218 kcs_chan = <3>;
0219 status = "disabled";
0220 };
0221 };
0222
0223 spi0: spi@200000 {
0224 compatible = "nuvoton,npcm750-pspi";
0225 reg = <0x200000 0x1000>;
0226 pinctrl-names = "default";
0227 pinctrl-0 = <&pspi1_pins>;
0228 #address-cells = <1>;
0229 #size-cells = <0>;
0230 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0231 clocks = <&clk NPCM7XX_CLK_APB5>;
0232 clock-names = "clk_apb5";
0233 resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;
0234 status = "disabled";
0235 };
0236
0237 spi1: spi@201000 {
0238 compatible = "nuvoton,npcm750-pspi";
0239 reg = <0x201000 0x1000>;
0240 pinctrl-names = "default";
0241 pinctrl-0 = <&pspi2_pins>;
0242 #address-cells = <1>;
0243 #size-cells = <0>;
0244 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0245 clocks = <&clk NPCM7XX_CLK_APB5>;
0246 clock-names = "clk_apb5";
0247 resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI2>;
0248 status = "disabled";
0249 };
0250
0251 timer0: timer@8000 {
0252 compatible = "nuvoton,npcm750-timer";
0253 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0254 reg = <0x8000 0x1C>;
0255 clocks = <&clk NPCM7XX_CLK_TIMER>;
0256 };
0257
0258 watchdog0: watchdog@801C {
0259 compatible = "nuvoton,npcm750-wdt";
0260 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
0261 reg = <0x801C 0x4>;
0262 status = "disabled";
0263 clocks = <&clk NPCM7XX_CLK_TIMER>;
0264 };
0265
0266 watchdog1: watchdog@901C {
0267 compatible = "nuvoton,npcm750-wdt";
0268 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0269 reg = <0x901C 0x4>;
0270 status = "disabled";
0271 clocks = <&clk NPCM7XX_CLK_TIMER>;
0272 };
0273
0274 watchdog2: watchdog@a01C {
0275 compatible = "nuvoton,npcm750-wdt";
0276 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0277 reg = <0xa01C 0x4>;
0278 status = "disabled";
0279 clocks = <&clk NPCM7XX_CLK_TIMER>;
0280 };
0281
0282 serial0: serial@1000 {
0283 compatible = "nuvoton,npcm750-uart";
0284 reg = <0x1000 0x1000>;
0285 clocks = <&clk NPCM7XX_CLK_UART>;
0286 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0287 reg-shift = <2>;
0288 status = "disabled";
0289 };
0290
0291 serial1: serial@2000 {
0292 compatible = "nuvoton,npcm750-uart";
0293 reg = <0x2000 0x1000>;
0294 clocks = <&clk NPCM7XX_CLK_UART>;
0295 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0296 reg-shift = <2>;
0297 status = "disabled";
0298 };
0299
0300 serial2: serial@3000 {
0301 compatible = "nuvoton,npcm750-uart";
0302 reg = <0x3000 0x1000>;
0303 clocks = <&clk NPCM7XX_CLK_UART>;
0304 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0305 reg-shift = <2>;
0306 status = "disabled";
0307 };
0308
0309 serial3: serial@4000 {
0310 compatible = "nuvoton,npcm750-uart";
0311 reg = <0x4000 0x1000>;
0312 clocks = <&clk NPCM7XX_CLK_UART>;
0313 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0314 reg-shift = <2>;
0315 status = "disabled";
0316 };
0317
0318 rng: rng@b000 {
0319 compatible = "nuvoton,npcm750-rng";
0320 reg = <0xb000 0x8>;
0321 status = "disabled";
0322 };
0323
0324 adc: adc@c000 {
0325 compatible = "nuvoton,npcm750-adc";
0326 reg = <0xc000 0x8>;
0327 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0328 clocks = <&clk NPCM7XX_CLK_ADC>;
0329 resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_ADC>;
0330 status = "disabled";
0331 };
0332
0333 pwm_fan: pwm-fan-controller@103000 {
0334 #address-cells = <1>;
0335 #size-cells = <0>;
0336 compatible = "nuvoton,npcm750-pwm-fan";
0337 reg = <0x103000 0x2000>, <0x180000 0x8000>;
0338 reg-names = "pwm", "fan";
0339 clocks = <&clk NPCM7XX_CLK_APB3>,
0340 <&clk NPCM7XX_CLK_APB4>;
0341 clock-names = "pwm","fan";
0342 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
0343 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
0344 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
0345 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
0346 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
0347 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
0348 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
0349 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0350 pinctrl-names = "default";
0351 pinctrl-0 = <&pwm0_pins &pwm1_pins
0352 &pwm2_pins &pwm3_pins
0353 &pwm4_pins &pwm5_pins
0354 &pwm6_pins &pwm7_pins
0355 &fanin0_pins &fanin1_pins
0356 &fanin2_pins &fanin3_pins
0357 &fanin4_pins &fanin5_pins
0358 &fanin6_pins &fanin7_pins
0359 &fanin8_pins &fanin9_pins
0360 &fanin10_pins &fanin11_pins
0361 &fanin12_pins &fanin13_pins
0362 &fanin14_pins &fanin15_pins>;
0363 status = "disabled";
0364 };
0365
0366 i2c0: i2c@80000 {
0367 reg = <0x80000 0x1000>;
0368 compatible = "nuvoton,npcm750-i2c";
0369 #address-cells = <1>;
0370 #size-cells = <0>;
0371 clocks = <&clk NPCM7XX_CLK_APB2>;
0372 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
0373 pinctrl-names = "default";
0374 pinctrl-0 = <&smb0_pins>;
0375 status = "disabled";
0376 };
0377
0378 i2c1: i2c@81000 {
0379 reg = <0x81000 0x1000>;
0380 compatible = "nuvoton,npcm750-i2c";
0381 #address-cells = <1>;
0382 #size-cells = <0>;
0383 clocks = <&clk NPCM7XX_CLK_APB2>;
0384 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0385 pinctrl-names = "default";
0386 pinctrl-0 = <&smb1_pins>;
0387 status = "disabled";
0388 };
0389
0390 i2c2: i2c@82000 {
0391 reg = <0x82000 0x1000>;
0392 compatible = "nuvoton,npcm750-i2c";
0393 #address-cells = <1>;
0394 #size-cells = <0>;
0395 clocks = <&clk NPCM7XX_CLK_APB2>;
0396 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0397 pinctrl-names = "default";
0398 pinctrl-0 = <&smb2_pins>;
0399 status = "disabled";
0400 };
0401
0402 i2c3: i2c@83000 {
0403 reg = <0x83000 0x1000>;
0404 compatible = "nuvoton,npcm750-i2c";
0405 #address-cells = <1>;
0406 #size-cells = <0>;
0407 clocks = <&clk NPCM7XX_CLK_APB2>;
0408 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0409 pinctrl-names = "default";
0410 pinctrl-0 = <&smb3_pins>;
0411 status = "disabled";
0412 };
0413
0414 i2c4: i2c@84000 {
0415 reg = <0x84000 0x1000>;
0416 compatible = "nuvoton,npcm750-i2c";
0417 #address-cells = <1>;
0418 #size-cells = <0>;
0419 clocks = <&clk NPCM7XX_CLK_APB2>;
0420 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
0421 pinctrl-names = "default";
0422 pinctrl-0 = <&smb4_pins>;
0423 status = "disabled";
0424 };
0425
0426 i2c5: i2c@85000 {
0427 reg = <0x85000 0x1000>;
0428 compatible = "nuvoton,npcm750-i2c";
0429 #address-cells = <1>;
0430 #size-cells = <0>;
0431 clocks = <&clk NPCM7XX_CLK_APB2>;
0432 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0433 pinctrl-names = "default";
0434 pinctrl-0 = <&smb5_pins>;
0435 status = "disabled";
0436 };
0437
0438 i2c6: i2c@86000 {
0439 reg = <0x86000 0x1000>;
0440 compatible = "nuvoton,npcm750-i2c";
0441 #address-cells = <1>;
0442 #size-cells = <0>;
0443 clocks = <&clk NPCM7XX_CLK_APB2>;
0444 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
0445 pinctrl-names = "default";
0446 pinctrl-0 = <&smb6_pins>;
0447 status = "disabled";
0448 };
0449
0450 i2c7: i2c@87000 {
0451 reg = <0x87000 0x1000>;
0452 compatible = "nuvoton,npcm750-i2c";
0453 #address-cells = <1>;
0454 #size-cells = <0>;
0455 clocks = <&clk NPCM7XX_CLK_APB2>;
0456 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0457 pinctrl-names = "default";
0458 pinctrl-0 = <&smb7_pins>;
0459 status = "disabled";
0460 };
0461
0462 i2c8: i2c@88000 {
0463 reg = <0x88000 0x1000>;
0464 compatible = "nuvoton,npcm750-i2c";
0465 #address-cells = <1>;
0466 #size-cells = <0>;
0467 clocks = <&clk NPCM7XX_CLK_APB2>;
0468 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0469 pinctrl-names = "default";
0470 pinctrl-0 = <&smb8_pins>;
0471 status = "disabled";
0472 };
0473
0474 i2c9: i2c@89000 {
0475 reg = <0x89000 0x1000>;
0476 compatible = "nuvoton,npcm750-i2c";
0477 #address-cells = <1>;
0478 #size-cells = <0>;
0479 clocks = <&clk NPCM7XX_CLK_APB2>;
0480 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0481 pinctrl-names = "default";
0482 pinctrl-0 = <&smb9_pins>;
0483 status = "disabled";
0484 };
0485
0486 i2c10: i2c@8a000 {
0487 reg = <0x8a000 0x1000>;
0488 compatible = "nuvoton,npcm750-i2c";
0489 #address-cells = <1>;
0490 #size-cells = <0>;
0491 clocks = <&clk NPCM7XX_CLK_APB2>;
0492 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0493 pinctrl-names = "default";
0494 pinctrl-0 = <&smb10_pins>;
0495 status = "disabled";
0496 };
0497
0498 i2c11: i2c@8b000 {
0499 reg = <0x8b000 0x1000>;
0500 compatible = "nuvoton,npcm750-i2c";
0501 #address-cells = <1>;
0502 #size-cells = <0>;
0503 clocks = <&clk NPCM7XX_CLK_APB2>;
0504 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0505 pinctrl-names = "default";
0506 pinctrl-0 = <&smb11_pins>;
0507 status = "disabled";
0508 };
0509
0510 i2c12: i2c@8c000 {
0511 reg = <0x8c000 0x1000>;
0512 compatible = "nuvoton,npcm750-i2c";
0513 #address-cells = <1>;
0514 #size-cells = <0>;
0515 clocks = <&clk NPCM7XX_CLK_APB2>;
0516 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0517 pinctrl-names = "default";
0518 pinctrl-0 = <&smb12_pins>;
0519 status = "disabled";
0520 };
0521
0522 i2c13: i2c@8d000 {
0523 reg = <0x8d000 0x1000>;
0524 compatible = "nuvoton,npcm750-i2c";
0525 #address-cells = <1>;
0526 #size-cells = <0>;
0527 clocks = <&clk NPCM7XX_CLK_APB2>;
0528 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0529 pinctrl-names = "default";
0530 pinctrl-0 = <&smb13_pins>;
0531 status = "disabled";
0532 };
0533
0534 i2c14: i2c@8e000 {
0535 reg = <0x8e000 0x1000>;
0536 compatible = "nuvoton,npcm750-i2c";
0537 #address-cells = <1>;
0538 #size-cells = <0>;
0539 clocks = <&clk NPCM7XX_CLK_APB2>;
0540 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
0541 pinctrl-names = "default";
0542 pinctrl-0 = <&smb14_pins>;
0543 status = "disabled";
0544 };
0545
0546 i2c15: i2c@8f000 {
0547 reg = <0x8f000 0x1000>;
0548 compatible = "nuvoton,npcm750-i2c";
0549 #address-cells = <1>;
0550 #size-cells = <0>;
0551 clocks = <&clk NPCM7XX_CLK_APB2>;
0552 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0553 pinctrl-names = "default";
0554 pinctrl-0 = <&smb15_pins>;
0555 status = "disabled";
0556 };
0557 };
0558 };
0559
0560 pinctrl: pinctrl@f0800000 {
0561 #address-cells = <1>;
0562 #size-cells = <1>;
0563 compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd";
0564 ranges = <0 0xf0010000 0x8000>;
0565 gpio0: gpio@f0010000 {
0566 gpio-controller;
0567 #gpio-cells = <2>;
0568 reg = <0x0 0x80>;
0569 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
0570 gpio-ranges = <&pinctrl 0 0 32>;
0571 };
0572 gpio1: gpio@f0011000 {
0573 gpio-controller;
0574 #gpio-cells = <2>;
0575 reg = <0x1000 0x80>;
0576 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0577 gpio-ranges = <&pinctrl 0 32 32>;
0578 };
0579 gpio2: gpio@f0012000 {
0580 gpio-controller;
0581 #gpio-cells = <2>;
0582 reg = <0x2000 0x80>;
0583 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
0584 gpio-ranges = <&pinctrl 0 64 32>;
0585 };
0586 gpio3: gpio@f0013000 {
0587 gpio-controller;
0588 #gpio-cells = <2>;
0589 reg = <0x3000 0x80>;
0590 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
0591 gpio-ranges = <&pinctrl 0 96 32>;
0592 };
0593 gpio4: gpio@f0014000 {
0594 gpio-controller;
0595 #gpio-cells = <2>;
0596 reg = <0x4000 0x80>;
0597 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
0598 gpio-ranges = <&pinctrl 0 128 32>;
0599 };
0600 gpio5: gpio@f0015000 {
0601 gpio-controller;
0602 #gpio-cells = <2>;
0603 reg = <0x5000 0x80>;
0604 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
0605 gpio-ranges = <&pinctrl 0 160 32>;
0606 };
0607 gpio6: gpio@f0016000 {
0608 gpio-controller;
0609 #gpio-cells = <2>;
0610 reg = <0x6000 0x80>;
0611 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
0612 gpio-ranges = <&pinctrl 0 192 32>;
0613 };
0614 gpio7: gpio@f0017000 {
0615 gpio-controller;
0616 #gpio-cells = <2>;
0617 reg = <0x7000 0x80>;
0618 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
0619 gpio-ranges = <&pinctrl 0 224 32>;
0620 };
0621
0622 iox1_pins: iox1-pins {
0623 groups = "iox1";
0624 function = "iox1";
0625 };
0626 iox2_pins: iox2-pins {
0627 groups = "iox2";
0628 function = "iox2";
0629 };
0630 smb1d_pins: smb1d-pins {
0631 groups = "smb1d";
0632 function = "smb1d";
0633 };
0634 smb2d_pins: smb2d-pins {
0635 groups = "smb2d";
0636 function = "smb2d";
0637 };
0638 lkgpo1_pins: lkgpo1-pins {
0639 groups = "lkgpo1";
0640 function = "lkgpo1";
0641 };
0642 lkgpo2_pins: lkgpo2-pins {
0643 groups = "lkgpo2";
0644 function = "lkgpo2";
0645 };
0646 ioxh_pins: ioxh-pins {
0647 groups = "ioxh";
0648 function = "ioxh";
0649 };
0650 gspi_pins: gspi-pins {
0651 groups = "gspi";
0652 function = "gspi";
0653 };
0654 smb5b_pins: smb5b-pins {
0655 groups = "smb5b";
0656 function = "smb5b";
0657 };
0658 smb5c_pins: smb5c-pins {
0659 groups = "smb5c";
0660 function = "smb5c";
0661 };
0662 lkgpo0_pins: lkgpo0-pins {
0663 groups = "lkgpo0";
0664 function = "lkgpo0";
0665 };
0666 pspi2_pins: pspi2-pins {
0667 groups = "pspi2";
0668 function = "pspi2";
0669 };
0670 smb4den_pins: smb4den-pins {
0671 groups = "smb4den";
0672 function = "smb4den";
0673 };
0674 smb4b_pins: smb4b-pins {
0675 groups = "smb4b";
0676 function = "smb4b";
0677 };
0678 smb4c_pins: smb4c-pins {
0679 groups = "smb4c";
0680 function = "smb4c";
0681 };
0682 smb15_pins: smb15-pins {
0683 groups = "smb15";
0684 function = "smb15";
0685 };
0686 smb4d_pins: smb4d-pins {
0687 groups = "smb4d";
0688 function = "smb4d";
0689 };
0690 smb14_pins: smb14-pins {
0691 groups = "smb14";
0692 function = "smb14";
0693 };
0694 smb5_pins: smb5-pins {
0695 groups = "smb5";
0696 function = "smb5";
0697 };
0698 smb4_pins: smb4-pins {
0699 groups = "smb4";
0700 function = "smb4";
0701 };
0702 smb3_pins: smb3-pins {
0703 groups = "smb3";
0704 function = "smb3";
0705 };
0706 spi0cs1_pins: spi0cs1-pins {
0707 groups = "spi0cs1";
0708 function = "spi0cs1";
0709 };
0710 spi0cs2_pins: spi0cs2-pins {
0711 groups = "spi0cs2";
0712 function = "spi0cs2";
0713 };
0714 spi0cs3_pins: spi0cs3-pins {
0715 groups = "spi0cs3";
0716 function = "spi0cs3";
0717 };
0718 smb3c_pins: smb3c-pins {
0719 groups = "smb3c";
0720 function = "smb3c";
0721 };
0722 smb3b_pins: smb3b-pins {
0723 groups = "smb3b";
0724 function = "smb3b";
0725 };
0726 bmcuart0a_pins: bmcuart0a-pins {
0727 groups = "bmcuart0a";
0728 function = "bmcuart0a";
0729 };
0730 uart1_pins: uart1-pins {
0731 groups = "uart1";
0732 function = "uart1";
0733 };
0734 jtag2_pins: jtag2-pins {
0735 groups = "jtag2";
0736 function = "jtag2";
0737 };
0738 bmcuart1_pins: bmcuart1-pins {
0739 groups = "bmcuart1";
0740 function = "bmcuart1";
0741 };
0742 uart2_pins: uart2-pins {
0743 groups = "uart2";
0744 function = "uart2";
0745 };
0746 bmcuart0b_pins: bmcuart0b-pins {
0747 groups = "bmcuart0b";
0748 function = "bmcuart0b";
0749 };
0750 r1err_pins: r1err-pins {
0751 groups = "r1err";
0752 function = "r1err";
0753 };
0754 r1md_pins: r1md-pins {
0755 groups = "r1md";
0756 function = "r1md";
0757 };
0758 smb3d_pins: smb3d-pins {
0759 groups = "smb3d";
0760 function = "smb3d";
0761 };
0762 fanin0_pins: fanin0-pins {
0763 groups = "fanin0";
0764 function = "fanin0";
0765 };
0766 fanin1_pins: fanin1-pins {
0767 groups = "fanin1";
0768 function = "fanin1";
0769 };
0770 fanin2_pins: fanin2-pins {
0771 groups = "fanin2";
0772 function = "fanin2";
0773 };
0774 fanin3_pins: fanin3-pins {
0775 groups = "fanin3";
0776 function = "fanin3";
0777 };
0778 fanin4_pins: fanin4-pins {
0779 groups = "fanin4";
0780 function = "fanin4";
0781 };
0782 fanin5_pins: fanin5-pins {
0783 groups = "fanin5";
0784 function = "fanin5";
0785 };
0786 fanin6_pins: fanin6-pins {
0787 groups = "fanin6";
0788 function = "fanin6";
0789 };
0790 fanin7_pins: fanin7-pins {
0791 groups = "fanin7";
0792 function = "fanin7";
0793 };
0794 fanin8_pins: fanin8-pins {
0795 groups = "fanin8";
0796 function = "fanin8";
0797 };
0798 fanin9_pins: fanin9-pins {
0799 groups = "fanin9";
0800 function = "fanin9";
0801 };
0802 fanin10_pins: fanin10-pins {
0803 groups = "fanin10";
0804 function = "fanin10";
0805 };
0806 fanin11_pins: fanin11-pins {
0807 groups = "fanin11";
0808 function = "fanin11";
0809 };
0810 fanin12_pins: fanin12-pins {
0811 groups = "fanin12";
0812 function = "fanin12";
0813 };
0814 fanin13_pins: fanin13-pins {
0815 groups = "fanin13";
0816 function = "fanin13";
0817 };
0818 fanin14_pins: fanin14-pins {
0819 groups = "fanin14";
0820 function = "fanin14";
0821 };
0822 fanin15_pins: fanin15-pins {
0823 groups = "fanin15";
0824 function = "fanin15";
0825 };
0826 pwm0_pins: pwm0-pins {
0827 groups = "pwm0";
0828 function = "pwm0";
0829 };
0830 pwm1_pins: pwm1-pins {
0831 groups = "pwm1";
0832 function = "pwm1";
0833 };
0834 pwm2_pins: pwm2-pins {
0835 groups = "pwm2";
0836 function = "pwm2";
0837 };
0838 pwm3_pins: pwm3-pins {
0839 groups = "pwm3";
0840 function = "pwm3";
0841 };
0842 r2_pins: r2-pins {
0843 groups = "r2";
0844 function = "r2";
0845 };
0846 r2err_pins: r2err-pins {
0847 groups = "r2err";
0848 function = "r2err";
0849 };
0850 r2md_pins: r2md-pins {
0851 groups = "r2md";
0852 function = "r2md";
0853 };
0854 ga20kbc_pins: ga20kbc-pins {
0855 groups = "ga20kbc";
0856 function = "ga20kbc";
0857 };
0858 smb5d_pins: smb5d-pins {
0859 groups = "smb5d";
0860 function = "smb5d";
0861 };
0862 lpc_pins: lpc-pins {
0863 groups = "lpc";
0864 function = "lpc";
0865 };
0866 espi_pins: espi-pins {
0867 groups = "espi";
0868 function = "espi";
0869 };
0870 rg1_pins: rg1-pins {
0871 groups = "rg1";
0872 function = "rg1";
0873 };
0874 rg1mdio_pins: rg1mdio-pins {
0875 groups = "rg1mdio";
0876 function = "rg1mdio";
0877 };
0878 rg2_pins: rg2-pins {
0879 groups = "rg2";
0880 function = "rg2";
0881 };
0882 ddr_pins: ddr-pins {
0883 groups = "ddr";
0884 function = "ddr";
0885 };
0886 smb0_pins: smb0-pins {
0887 groups = "smb0";
0888 function = "smb0";
0889 };
0890 smb1_pins: smb1-pins {
0891 groups = "smb1";
0892 function = "smb1";
0893 };
0894 smb2_pins: smb2-pins {
0895 groups = "smb2";
0896 function = "smb2";
0897 };
0898 smb2c_pins: smb2c-pins {
0899 groups = "smb2c";
0900 function = "smb2c";
0901 };
0902 smb2b_pins: smb2b-pins {
0903 groups = "smb2b";
0904 function = "smb2b";
0905 };
0906 smb1c_pins: smb1c-pins {
0907 groups = "smb1c";
0908 function = "smb1c";
0909 };
0910 smb1b_pins: smb1b-pins {
0911 groups = "smb1b";
0912 function = "smb1b";
0913 };
0914 smb8_pins: smb8-pins {
0915 groups = "smb8";
0916 function = "smb8";
0917 };
0918 smb9_pins: smb9-pins {
0919 groups = "smb9";
0920 function = "smb9";
0921 };
0922 smb10_pins: smb10-pins {
0923 groups = "smb10";
0924 function = "smb10";
0925 };
0926 smb11_pins: smb11-pins {
0927 groups = "smb11";
0928 function = "smb11";
0929 };
0930 sd1_pins: sd1-pins {
0931 groups = "sd1";
0932 function = "sd1";
0933 };
0934 sd1pwr_pins: sd1pwr-pins {
0935 groups = "sd1pwr";
0936 function = "sd1pwr";
0937 };
0938 pwm4_pins: pwm4-pins {
0939 groups = "pwm4";
0940 function = "pwm4";
0941 };
0942 pwm5_pins: pwm5-pins {
0943 groups = "pwm5";
0944 function = "pwm5";
0945 };
0946 pwm6_pins: pwm6-pins {
0947 groups = "pwm6";
0948 function = "pwm6";
0949 };
0950 pwm7_pins: pwm7-pins {
0951 groups = "pwm7";
0952 function = "pwm7";
0953 };
0954 mmc8_pins: mmc8-pins {
0955 groups = "mmc8";
0956 function = "mmc8";
0957 };
0958 mmc_pins: mmc-pins {
0959 groups = "mmc";
0960 function = "mmc";
0961 };
0962 mmcwp_pins: mmcwp-pins {
0963 groups = "mmcwp";
0964 function = "mmcwp";
0965 };
0966 mmccd_pins: mmccd-pins {
0967 groups = "mmccd";
0968 function = "mmccd";
0969 };
0970 mmcrst_pins: mmcrst-pins {
0971 groups = "mmcrst";
0972 function = "mmcrst";
0973 };
0974 clkout_pins: clkout-pins {
0975 groups = "clkout";
0976 function = "clkout";
0977 };
0978 serirq_pins: serirq-pins {
0979 groups = "serirq";
0980 function = "serirq";
0981 };
0982 lpcclk_pins: lpcclk-pins {
0983 groups = "lpcclk";
0984 function = "lpcclk";
0985 };
0986 scipme_pins: scipme-pins {
0987 groups = "scipme";
0988 function = "scipme";
0989 };
0990 sci_pins: sci-pins {
0991 groups = "sci";
0992 function = "sci";
0993 };
0994 smb6_pins: smb6-pins {
0995 groups = "smb6";
0996 function = "smb6";
0997 };
0998 smb7_pins: smb7-pins {
0999 groups = "smb7";
1000 function = "smb7";
1001 };
1002 pspi1_pins: pspi1-pins {
1003 groups = "pspi1";
1004 function = "pspi1";
1005 };
1006 faninx_pins: faninx-pins {
1007 groups = "faninx";
1008 function = "faninx";
1009 };
1010 r1_pins: r1-pins {
1011 groups = "r1";
1012 function = "r1";
1013 };
1014 spi3_pins: spi3-pins {
1015 groups = "spi3";
1016 function = "spi3";
1017 };
1018 spi3cs1_pins: spi3cs1-pins {
1019 groups = "spi3cs1";
1020 function = "spi3cs1";
1021 };
1022 spi3quad_pins: spi3quad-pins {
1023 groups = "spi3quad";
1024 function = "spi3quad";
1025 };
1026 spi3cs2_pins: spi3cs2-pins {
1027 groups = "spi3cs2";
1028 function = "spi3cs2";
1029 };
1030 spi3cs3_pins: spi3cs3-pins {
1031 groups = "spi3cs3";
1032 function = "spi3cs3";
1033 };
1034 nprd_smi_pins: nprd-smi-pins {
1035 groups = "nprd_smi";
1036 function = "nprd_smi";
1037 };
1038 smb0b_pins: smb0b-pins {
1039 groups = "smb0b";
1040 function = "smb0b";
1041 };
1042 smb0c_pins: smb0c-pins {
1043 groups = "smb0c";
1044 function = "smb0c";
1045 };
1046 smb0den_pins: smb0den-pins {
1047 groups = "smb0den";
1048 function = "smb0den";
1049 };
1050 smb0d_pins: smb0d-pins {
1051 groups = "smb0d";
1052 function = "smb0d";
1053 };
1054 ddc_pins: ddc-pins {
1055 groups = "ddc";
1056 function = "ddc";
1057 };
1058 rg2mdio_pins: rg2mdio-pins {
1059 groups = "rg2mdio";
1060 function = "rg2mdio";
1061 };
1062 wdog1_pins: wdog1-pins {
1063 groups = "wdog1";
1064 function = "wdog1";
1065 };
1066 wdog2_pins: wdog2-pins {
1067 groups = "wdog2";
1068 function = "wdog2";
1069 };
1070 smb12_pins: smb12-pins {
1071 groups = "smb12";
1072 function = "smb12";
1073 };
1074 smb13_pins: smb13-pins {
1075 groups = "smb13";
1076 function = "smb13";
1077 };
1078 spix_pins: spix-pins {
1079 groups = "spix";
1080 function = "spix";
1081 };
1082 spixcs1_pins: spixcs1-pins {
1083 groups = "spixcs1";
1084 function = "spixcs1";
1085 };
1086 clkreq_pins: clkreq-pins {
1087 groups = "clkreq";
1088 function = "clkreq";
1089 };
1090 hgpio0_pins: hgpio0-pins {
1091 groups = "hgpio0";
1092 function = "hgpio0";
1093 };
1094 hgpio1_pins: hgpio1-pins {
1095 groups = "hgpio1";
1096 function = "hgpio1";
1097 };
1098 hgpio2_pins: hgpio2-pins {
1099 groups = "hgpio2";
1100 function = "hgpio2";
1101 };
1102 hgpio3_pins: hgpio3-pins {
1103 groups = "hgpio3";
1104 function = "hgpio3";
1105 };
1106 hgpio4_pins: hgpio4-pins {
1107 groups = "hgpio4";
1108 function = "hgpio4";
1109 };
1110 hgpio5_pins: hgpio5-pins {
1111 groups = "hgpio5";
1112 function = "hgpio5";
1113 };
1114 hgpio6_pins: hgpio6-pins {
1115 groups = "hgpio6";
1116 function = "hgpio6";
1117 };
1118 hgpio7_pins: hgpio7-pins {
1119 groups = "hgpio7";
1120 function = "hgpio7";
1121 };
1122 };
1123 };
