0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * linux/arch/arm/boot/nspire.dtsi
0004 *
0005 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
0006 */
0007
0008 / {
0009 #address-cells = <1>;
0010 #size-cells = <1>;
0011 interrupt-parent = <&intc>;
0012
0013 cpus {
0014 cpu@0 {
0015 compatible = "arm,arm926ej-s";
0016 };
0017 };
0018
0019 bootrom: bootrom@0 {
0020 reg = <0x00000000 0x80000>;
0021 };
0022
0023 sram: sram@a4000000 {
0024 device = "memory";
0025 reg = <0xa4000000 0x20000>;
0026 };
0027
0028 timer_clk: timer_clk {
0029 #clock-cells = <0>;
0030 compatible = "fixed-clock";
0031 clock-frequency = <32768>;
0032 };
0033
0034 base_clk: base_clk {
0035 #clock-cells = <0>;
0036 reg = <0x900b0024 0x4>;
0037 };
0038
0039 ahb_clk: ahb_clk {
0040 #clock-cells = <0>;
0041 reg = <0x900b0024 0x4>;
0042 clocks = <&base_clk>;
0043 };
0044
0045 apb_pclk: apb_pclk {
0046 #clock-cells = <0>;
0047 compatible = "fixed-factor-clock";
0048 clock-div = <2>;
0049 clock-mult = <1>;
0050 clocks = <&ahb_clk>;
0051 };
0052
0053 usb_phy: usb_phy {
0054 compatible = "usb-nop-xceiv";
0055 #phy-cells = <0>;
0056 };
0057
0058 vbus_reg: vbus_reg {
0059 compatible = "regulator-fixed";
0060
0061 regulator-name = "USB VBUS output";
0062 regulator-type = "voltage";
0063
0064 regulator-min-microvolt = <5000000>;
0065 regulator-max-microvolt = <5000000>;
0066 };
0067
0068 ahb {
0069 compatible = "simple-bus";
0070 #address-cells = <1>;
0071 #size-cells = <1>;
0072 ranges;
0073
0074 spi: spi@a9000000 {
0075 reg = <0xa9000000 0x1000>;
0076 };
0077
0078 usb0: usb@b0000000 {
0079 compatible = "lsi,zevio-usb";
0080 reg = <0xb0000000 0x1000>;
0081 interrupts = <8>;
0082
0083 usb-phy = <&usb_phy>;
0084 vbus-supply = <&vbus_reg>;
0085 };
0086
0087 usb1: usb@b4000000 {
0088 reg = <0xb4000000 0x1000>;
0089 interrupts = <9>;
0090 status = "disabled";
0091 };
0092
0093 lcd: lcd@c0000000 {
0094 compatible = "arm,pl111", "arm,primecell";
0095 reg = <0xc0000000 0x1000>;
0096 interrupts = <21>;
0097
0098 /*
0099 * We assume the same clock is fed to APB and CLCDCLK.
0100 * There is some code to scale the clock down by a factor
0101 * 48 for the display so likely the frequency to the
0102 * display is 1MHz and the CLCDCLK is 48 MHz.
0103 */
0104 clocks = <&apb_pclk>, <&apb_pclk>;
0105 clock-names = "clcdclk", "apb_pclk";
0106 };
0107
0108 adc: adc@c4000000 {
0109 reg = <0xc4000000 0x1000>;
0110 interrupts = <11>;
0111 };
0112
0113 tdes: crypto@c8010000 {
0114 reg = <0xc8010000 0x1000>;
0115 };
0116
0117 sha256: crypto@cc000000 {
0118 reg = <0xcc000000 0x1000>;
0119 };
0120
0121 apb@90000000 {
0122 compatible = "simple-bus";
0123 #address-cells = <1>;
0124 #size-cells = <1>;
0125 clock-ranges;
0126 ranges;
0127
0128 gpio: gpio@90000000 {
0129 compatible = "lsi,zevio-gpio";
0130 reg = <0x90000000 0x1000>;
0131 interrupts = <7>;
0132 gpio-controller;
0133 #gpio-cells = <2>;
0134 };
0135
0136 fast_timer: timer@90010000 {
0137 reg = <0x90010000 0x1000>;
0138 interrupts = <17>;
0139 };
0140
0141 uart: serial@90020000 {
0142 reg = <0x90020000 0x1000>;
0143 interrupts = <1>;
0144 };
0145
0146 timer0: timer@900c0000 {
0147 reg = <0x900c0000 0x1000>;
0148 clocks = <&timer_clk>, <&timer_clk>,
0149 <&timer_clk>;
0150 clock-names = "timer0clk", "timer1clk",
0151 "apb_pclk";
0152 };
0153
0154 timer1: timer@900d0000 {
0155 reg = <0x900d0000 0x1000>;
0156 interrupts = <19>;
0157 clocks = <&timer_clk>, <&timer_clk>,
0158 <&timer_clk>;
0159 clock-names = "timer0clk", "timer1clk",
0160 "apb_pclk";
0161 };
0162
0163 watchdog: watchdog@90060000 {
0164 compatible = "arm,amba-primecell";
0165 reg = <0x90060000 0x1000>;
0166 interrupts = <3>;
0167 };
0168
0169 rtc: rtc@90090000 {
0170 reg = <0x90090000 0x1000>;
0171 interrupts = <4>;
0172 };
0173
0174 misc: misc@900a0000 {
0175 reg = <0x900a0000 0x1000>;
0176 };
0177
0178 pwr: pwr@900b0000 {
0179 reg = <0x900b0000 0x1000>;
0180 interrupts = <15>;
0181 };
0182
0183 keypad: input@900e0000 {
0184 compatible = "ti,nspire-keypad";
0185 reg = <0x900e0000 0x1000>;
0186 interrupts = <16>;
0187
0188 scan-interval = <1000>;
0189 row-delay = <200>;
0190
0191 clocks = <&apb_pclk>;
0192 };
0193
0194 contrast: contrast@900f0000 {
0195 reg = <0x900f0000 0x1000>;
0196 };
0197
0198 led: led@90110000 {
0199 reg = <0x90110000 0x1000>;
0200 };
0201 };
0202 };
0203 };
