0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (c) 2014 MediaTek Inc.
0004 * Author: Joe.C <yingjoe.chen@mediatek.com>
0005 *
0006 */
0007
0008 #include <dt-bindings/clock/mt8135-clk.h>
0009 #include <dt-bindings/interrupt-controller/irq.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/reset/mt8135-resets.h>
0012 #include <dt-bindings/pinctrl/mt8135-pinfunc.h>
0013
0014 / {
0015 #address-cells = <2>;
0016 #size-cells = <2>;
0017 compatible = "mediatek,mt8135";
0018 interrupt-parent = <&sysirq>;
0019
0020 cpu-map {
0021 cluster0 {
0022 core0 {
0023 cpu = <&cpu0>;
0024 };
0025 core1 {
0026 cpu = <&cpu1>;
0027 };
0028 };
0029
0030 cluster1 {
0031 core0 {
0032 cpu = <&cpu2>;
0033 };
0034 core1 {
0035 cpu = <&cpu3>;
0036 };
0037 };
0038 };
0039
0040 cpus {
0041 #address-cells = <1>;
0042 #size-cells = <0>;
0043 enable-method = "mediatek,mt81xx-tz-smp";
0044
0045 cpu0: cpu@0 {
0046 device_type = "cpu";
0047 compatible = "arm,cortex-a7";
0048 reg = <0x000>;
0049 };
0050
0051 cpu1: cpu@1 {
0052 device_type = "cpu";
0053 compatible = "arm,cortex-a7";
0054 reg = <0x001>;
0055 };
0056
0057 cpu2: cpu@100 {
0058 device_type = "cpu";
0059 compatible = "arm,cortex-a15";
0060 reg = <0x100>;
0061 };
0062
0063 cpu3: cpu@101 {
0064 device_type = "cpu";
0065 compatible = "arm,cortex-a15";
0066 reg = <0x101>;
0067 };
0068 };
0069
0070 reserved-memory {
0071 #address-cells = <2>;
0072 #size-cells = <2>;
0073 ranges;
0074
0075 trustzone-bootinfo@80002000 {
0076 compatible = "mediatek,trustzone-bootinfo";
0077 reg = <0 0x80002000 0 0x1000>;
0078 };
0079 };
0080
0081 clocks {
0082 #address-cells = <2>;
0083 #size-cells = <2>;
0084 compatible = "simple-bus";
0085 ranges;
0086
0087 system_clk: dummy13m {
0088 compatible = "fixed-clock";
0089 clock-frequency = <13000000>;
0090 #clock-cells = <0>;
0091 };
0092
0093 rtc_clk: dummy32k {
0094 compatible = "fixed-clock";
0095 clock-frequency = <32000>;
0096 #clock-cells = <0>;
0097 };
0098
0099 clk26m: clk26m {
0100 compatible = "fixed-clock";
0101 #clock-cells = <0>;
0102 clock-frequency = <26000000>;
0103 };
0104 };
0105
0106 timer {
0107 compatible = "arm,armv7-timer";
0108 interrupt-parent = <&gic>;
0109 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
0110 IRQ_TYPE_LEVEL_LOW)>,
0111 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
0112 IRQ_TYPE_LEVEL_LOW)>,
0113 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
0114 IRQ_TYPE_LEVEL_LOW)>,
0115 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
0116 IRQ_TYPE_LEVEL_LOW)>;
0117 clock-frequency = <13000000>;
0118 arm,cpu-registers-not-fw-configured;
0119 };
0120
0121 soc {
0122 #address-cells = <2>;
0123 #size-cells = <2>;
0124 compatible = "simple-bus";
0125 ranges;
0126
0127 topckgen: topckgen@10000000 {
0128 compatible = "mediatek,mt8135-topckgen";
0129 reg = <0 0x10000000 0 0x1000>;
0130 #clock-cells = <1>;
0131 };
0132
0133 infracfg: infracfg@10001000 {
0134 #reset-cells = <1>;
0135 #clock-cells = <1>;
0136 compatible = "mediatek,mt8135-infracfg", "syscon";
0137 reg = <0 0x10001000 0 0x1000>;
0138 };
0139
0140 pericfg: pericfg@10003000 {
0141 #reset-cells = <1>;
0142 #clock-cells = <1>;
0143 compatible = "mediatek,mt8135-pericfg", "syscon";
0144 reg = <0 0x10003000 0 0x1000>;
0145 };
0146
0147 /*
0148 * Pinctrl access register at 0x10005000 and 0x1020c000 through
0149 * regmap. Register 0x1000b000 is used by EINT.
0150 */
0151 pio: pinctrl@10005000 {
0152 compatible = "mediatek,mt8135-pinctrl";
0153 reg = <0 0x1000b000 0 0x1000>;
0154 mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
0155 pins-are-numbered;
0156 gpio-controller;
0157 #gpio-cells = <2>;
0158 interrupt-controller;
0159 #interrupt-cells = <2>;
0160 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
0161 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
0162 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
0163 };
0164
0165 syscfg_pctl_a: syscfg_pctl_a@10005000 {
0166 compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
0167 reg = <0 0x10005000 0 0x1000>;
0168 };
0169
0170 timer: timer@10008000 {
0171 compatible = "mediatek,mt8135-timer",
0172 "mediatek,mt6577-timer";
0173 reg = <0 0x10008000 0 0x80>;
0174 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
0175 clocks = <&system_clk>, <&rtc_clk>;
0176 clock-names = "system-clk", "rtc-clk";
0177 };
0178
0179 pwrap: pwrap@1000f000 {
0180 compatible = "mediatek,mt8135-pwrap";
0181 reg = <0 0x1000f000 0 0x1000>,
0182 <0 0x11017000 0 0x1000>;
0183 reg-names = "pwrap", "pwrap-bridge";
0184 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
0185 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
0186 <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
0187 reset-names = "pwrap", "pwrap-bridge";
0188 clocks = <&clk26m>, <&clk26m>;
0189 clock-names = "spi", "wrap";
0190 };
0191
0192 sysirq: interrupt-controller@10200030 {
0193 compatible = "mediatek,mt8135-sysirq",
0194 "mediatek,mt6577-sysirq";
0195 interrupt-controller;
0196 #interrupt-cells = <3>;
0197 interrupt-parent = <&gic>;
0198 reg = <0 0x10200030 0 0x1c>;
0199 };
0200
0201 apmixedsys: apmixedsys@10209000 {
0202 compatible = "mediatek,mt8135-apmixedsys";
0203 reg = <0 0x10209000 0 0x1000>;
0204 #clock-cells = <1>;
0205 };
0206
0207 syscfg_pctl_b: syscfg_pctl_b@1020c000 {
0208 compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
0209 reg = <0 0x1020c000 0 0x1000>;
0210 };
0211
0212 gic: interrupt-controller@10211000 {
0213 compatible = "arm,cortex-a15-gic";
0214 interrupt-controller;
0215 #interrupt-cells = <3>;
0216 interrupt-parent = <&gic>;
0217 reg = <0 0x10211000 0 0x1000>,
0218 <0 0x10212000 0 0x2000>,
0219 <0 0x10214000 0 0x2000>,
0220 <0 0x10216000 0 0x2000>;
0221 };
0222
0223 uart0: serial@11006000 {
0224 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
0225 reg = <0 0x11006000 0 0x400>;
0226 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
0227 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
0228 clock-names = "baud", "bus";
0229 status = "disabled";
0230 };
0231
0232 uart1: serial@11007000 {
0233 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
0234 reg = <0 0x11007000 0 0x400>;
0235 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
0236 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
0237 clock-names = "baud", "bus";
0238 status = "disabled";
0239 };
0240
0241 uart2: serial@11008000 {
0242 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
0243 reg = <0 0x11008000 0 0x400>;
0244 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
0245 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
0246 clock-names = "baud", "bus";
0247 status = "disabled";
0248 };
0249
0250 uart3: serial@11009000 {
0251 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
0252 reg = <0 0x11009000 0 0x400>;
0253 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
0254 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
0255 clock-names = "baud", "bus";
0256 status = "disabled";
0257 };
0258
0259 };
0260 };
