0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (c) 2014 MediaTek Inc.
0004 * Author: Joe.C <yingjoe.chen@mediatek.com>
0005 *
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010
0011 / {
0012 #address-cells = <2>;
0013 #size-cells = <2>;
0014 compatible = "mediatek,mt8127";
0015 interrupt-parent = <&sysirq>;
0016
0017 cpus {
0018 #address-cells = <1>;
0019 #size-cells = <0>;
0020 enable-method = "mediatek,mt81xx-tz-smp";
0021
0022 cpu@0 {
0023 device_type = "cpu";
0024 compatible = "arm,cortex-a7";
0025 reg = <0x0>;
0026 };
0027 cpu@1 {
0028 device_type = "cpu";
0029 compatible = "arm,cortex-a7";
0030 reg = <0x1>;
0031 };
0032 cpu@2 {
0033 device_type = "cpu";
0034 compatible = "arm,cortex-a7";
0035 reg = <0x2>;
0036 };
0037 cpu@3 {
0038 device_type = "cpu";
0039 compatible = "arm,cortex-a7";
0040 reg = <0x3>;
0041 };
0042
0043 };
0044
0045 reserved-memory {
0046 #address-cells = <2>;
0047 #size-cells = <2>;
0048 ranges;
0049
0050 trustzone-bootinfo@80002000 {
0051 compatible = "mediatek,trustzone-bootinfo";
0052 reg = <0 0x80002000 0 0x1000>;
0053 };
0054 };
0055
0056 clocks {
0057 #address-cells = <2>;
0058 #size-cells = <2>;
0059 compatible = "simple-bus";
0060 ranges;
0061
0062 system_clk: dummy13m {
0063 compatible = "fixed-clock";
0064 clock-frequency = <13000000>;
0065 #clock-cells = <0>;
0066 };
0067
0068 rtc_clk: dummy32k {
0069 compatible = "fixed-clock";
0070 clock-frequency = <32000>;
0071 #clock-cells = <0>;
0072 };
0073
0074 uart_clk: dummy26m {
0075 compatible = "fixed-clock";
0076 clock-frequency = <26000000>;
0077 #clock-cells = <0>;
0078 };
0079 };
0080
0081 timer {
0082 compatible = "arm,armv7-timer";
0083 interrupt-parent = <&gic>;
0084 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
0085 IRQ_TYPE_LEVEL_LOW)>,
0086 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
0087 IRQ_TYPE_LEVEL_LOW)>,
0088 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
0089 IRQ_TYPE_LEVEL_LOW)>,
0090 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
0091 IRQ_TYPE_LEVEL_LOW)>;
0092 clock-frequency = <13000000>;
0093 arm,cpu-registers-not-fw-configured;
0094 };
0095
0096 soc {
0097 #address-cells = <2>;
0098 #size-cells = <2>;
0099 compatible = "simple-bus";
0100 ranges;
0101
0102 timer: timer@10008000 {
0103 compatible = "mediatek,mt8127-timer",
0104 "mediatek,mt6577-timer";
0105 reg = <0 0x10008000 0 0x80>;
0106 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
0107 clocks = <&system_clk>, <&rtc_clk>;
0108 clock-names = "system-clk", "rtc-clk";
0109 };
0110
0111 sysirq: interrupt-controller@10200100 {
0112 compatible = "mediatek,mt8127-sysirq",
0113 "mediatek,mt6577-sysirq";
0114 interrupt-controller;
0115 #interrupt-cells = <3>;
0116 interrupt-parent = <&gic>;
0117 reg = <0 0x10200100 0 0x1c>;
0118 };
0119
0120 gic: interrupt-controller@10211000 {
0121 compatible = "arm,cortex-a7-gic";
0122 interrupt-controller;
0123 #interrupt-cells = <3>;
0124 interrupt-parent = <&gic>;
0125 reg = <0 0x10211000 0 0x1000>,
0126 <0 0x10212000 0 0x2000>,
0127 <0 0x10214000 0 0x2000>,
0128 <0 0x10216000 0 0x2000>;
0129 };
0130
0131 uart0: serial@11002000 {
0132 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
0133 reg = <0 0x11002000 0 0x400>;
0134 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
0135 clocks = <&uart_clk>;
0136 status = "disabled";
0137 };
0138
0139 uart1: serial@11003000 {
0140 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
0141 reg = <0 0x11003000 0 0x400>;
0142 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
0143 clocks = <&uart_clk>;
0144 status = "disabled";
0145 };
0146
0147 uart2: serial@11004000 {
0148 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
0149 reg = <0 0x11004000 0 0x400>;
0150 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
0151 clocks = <&uart_clk>;
0152 status = "disabled";
0153 };
0154
0155 uart3: serial@11005000 {
0156 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
0157 reg = <0 0x11005000 0 0x400>;
0158 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
0159 clocks = <&uart_clk>;
0160 status = "disabled";
0161 };
0162 };
0163 };
