0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (c) 2019 MediaTek Inc.
0004 *
0005 * Author: Ryder Lee <ryder.lee@mediatek.com>
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/clock/mt7629-clk.h>
0011 #include <dt-bindings/power/mt7622-power.h>
0012 #include <dt-bindings/gpio/gpio.h>
0013 #include <dt-bindings/phy/phy.h>
0014 #include <dt-bindings/reset/mt7629-resets.h>
0015
0016 / {
0017 compatible = "mediatek,mt7629";
0018 interrupt-parent = <&sysirq>;
0019 #address-cells = <1>;
0020 #size-cells = <1>;
0021
0022 cpus {
0023 #address-cells = <1>;
0024 #size-cells = <0>;
0025 enable-method = "mediatek,mt6589-smp";
0026
0027 cpu0: cpu@0 {
0028 device_type = "cpu";
0029 compatible = "arm,cortex-a7";
0030 reg = <0x0>;
0031 clock-frequency = <1250000000>;
0032 cci-control-port = <&cci_control2>;
0033 };
0034
0035 cpu1: cpu@1 {
0036 device_type = "cpu";
0037 compatible = "arm,cortex-a7";
0038 reg = <0x1>;
0039 clock-frequency = <1250000000>;
0040 cci-control-port = <&cci_control2>;
0041 };
0042 };
0043
0044 pmu {
0045 compatible = "arm,cortex-a7-pmu";
0046 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
0047 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
0048 interrupt-affinity = <&cpu0>, <&cpu1>;
0049 };
0050
0051 clk20m: oscillator-0 {
0052 compatible = "fixed-clock";
0053 #clock-cells = <0>;
0054 clock-frequency = <20000000>;
0055 clock-output-names = "clk20m";
0056 };
0057
0058 clk40m: oscillator-1 {
0059 compatible = "fixed-clock";
0060 #clock-cells = <0>;
0061 clock-frequency = <40000000>;
0062 clock-output-names = "clkxtal";
0063 };
0064
0065 timer {
0066 compatible = "arm,armv7-timer";
0067 interrupt-parent = <&gic>;
0068 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0069 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0070 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0071 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0072 clock-frequency = <20000000>;
0073 };
0074
0075 soc {
0076 compatible = "simple-bus";
0077 #address-cells = <1>;
0078 #size-cells = <1>;
0079 ranges;
0080
0081 infracfg: syscon@10000000 {
0082 compatible = "mediatek,mt7629-infracfg", "syscon";
0083 reg = <0x10000000 0x1000>;
0084 #clock-cells = <1>;
0085 };
0086
0087 pericfg: syscon@10002000 {
0088 compatible = "mediatek,mt7629-pericfg", "syscon";
0089 reg = <0x10002000 0x1000>;
0090 #clock-cells = <1>;
0091 };
0092
0093 scpsys: power-controller@10006000 {
0094 compatible = "mediatek,mt7629-scpsys",
0095 "mediatek,mt7622-scpsys";
0096 #power-domain-cells = <1>;
0097 reg = <0x10006000 0x1000>;
0098 clocks = <&topckgen CLK_TOP_HIF_SEL>;
0099 clock-names = "hif_sel";
0100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
0101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
0102 infracfg = <&infracfg>;
0103 };
0104
0105 timer: timer@10009000 {
0106 compatible = "mediatek,mt7629-timer",
0107 "mediatek,mt6765-timer";
0108 reg = <0x10009000 0x60>;
0109 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
0110 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
0111 clocks = <&clk20m>;
0112 clock-names = "clk20m";
0113 };
0114
0115 sysirq: interrupt-controller@10200a80 {
0116 compatible = "mediatek,mt7629-sysirq",
0117 "mediatek,mt6577-sysirq";
0118 reg = <0x10200a80 0x20>;
0119 interrupt-controller;
0120 #interrupt-cells = <3>;
0121 interrupt-parent = <&gic>;
0122 };
0123
0124 apmixedsys: syscon@10209000 {
0125 compatible = "mediatek,mt7629-apmixedsys", "syscon";
0126 reg = <0x10209000 0x1000>;
0127 #clock-cells = <1>;
0128 };
0129
0130 rng: rng@1020f000 {
0131 compatible = "mediatek,mt7629-rng",
0132 "mediatek,mt7623-rng";
0133 reg = <0x1020f000 0x100>;
0134 clocks = <&infracfg CLK_INFRA_TRNG_PD>;
0135 clock-names = "rng";
0136 };
0137
0138 topckgen: syscon@10210000 {
0139 compatible = "mediatek,mt7629-topckgen", "syscon";
0140 reg = <0x10210000 0x1000>;
0141 #clock-cells = <1>;
0142 };
0143
0144 watchdog: watchdog@10212000 {
0145 compatible = "mediatek,mt7629-wdt",
0146 "mediatek,mt6589-wdt";
0147 reg = <0x10212000 0x100>;
0148 };
0149
0150 pio: pinctrl@10217000 {
0151 compatible = "mediatek,mt7629-pinctrl";
0152 reg = <0x10217000 0x8000>,
0153 <0x10005000 0x1000>;
0154 reg-names = "base", "eint";
0155 gpio-controller;
0156 gpio-ranges = <&pio 0 0 79>;
0157 #gpio-cells = <2>;
0158 #interrupt-cells = <2>;
0159 interrupt-controller;
0160 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
0161 interrupt-parent = <&gic>;
0162 };
0163
0164 gic: interrupt-controller@10300000 {
0165 compatible = "arm,gic-400";
0166 interrupt-controller;
0167 #interrupt-cells = <3>;
0168 interrupt-parent = <&gic>;
0169 reg = <0x10310000 0x1000>,
0170 <0x10320000 0x1000>,
0171 <0x10340000 0x2000>,
0172 <0x10360000 0x2000>;
0173 };
0174
0175 cci: cci@10390000 {
0176 compatible = "arm,cci-400";
0177 #address-cells = <1>;
0178 #size-cells = <1>;
0179 reg = <0x10390000 0x1000>;
0180 ranges = <0 0x10390000 0x10000>;
0181
0182 cci_control0: slave-if@1000 {
0183 compatible = "arm,cci-400-ctrl-if";
0184 interface-type = "ace-lite";
0185 reg = <0x1000 0x1000>;
0186 };
0187
0188 cci_control1: slave-if@4000 {
0189 compatible = "arm,cci-400-ctrl-if";
0190 interface-type = "ace";
0191 reg = <0x4000 0x1000>;
0192 };
0193
0194 cci_control2: slave-if@5000 {
0195 compatible = "arm,cci-400-ctrl-if";
0196 interface-type = "ace";
0197 reg = <0x5000 0x1000>;
0198 };
0199
0200 pmu@9000 {
0201 compatible = "arm,cci-400-pmu,r1";
0202 reg = <0x9000 0x5000>;
0203 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
0204 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
0205 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
0206 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
0207 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0208 };
0209 };
0210
0211 uart0: serial@11002000 {
0212 compatible = "mediatek,mt7629-uart",
0213 "mediatek,mt6577-uart";
0214 reg = <0x11002000 0x400>;
0215 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
0216 clocks = <&topckgen CLK_TOP_UART_SEL>,
0217 <&pericfg CLK_PERI_UART0_PD>;
0218 clock-names = "baud", "bus";
0219 status = "disabled";
0220 };
0221
0222 uart1: serial@11003000 {
0223 compatible = "mediatek,mt7629-uart",
0224 "mediatek,mt6577-uart";
0225 reg = <0x11003000 0x400>;
0226 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
0227 clocks = <&topckgen CLK_TOP_UART_SEL>,
0228 <&pericfg CLK_PERI_UART1_PD>;
0229 clock-names = "baud", "bus";
0230 status = "disabled";
0231 };
0232
0233 uart2: serial@11004000 {
0234 compatible = "mediatek,mt7629-uart",
0235 "mediatek,mt6577-uart";
0236 reg = <0x11004000 0x400>;
0237 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
0238 clocks = <&topckgen CLK_TOP_UART_SEL>,
0239 <&pericfg CLK_PERI_UART2_PD>;
0240 clock-names = "baud", "bus";
0241 status = "disabled";
0242 };
0243
0244 pwm: pwm@11006000 {
0245 compatible = "mediatek,mt7629-pwm";
0246 reg = <0x11006000 0x1000>;
0247 #pwm-cells = <2>;
0248 clocks = <&topckgen CLK_TOP_PWM_SEL>,
0249 <&pericfg CLK_PERI_PWM_PD>,
0250 <&pericfg CLK_PERI_PWM1_PD>;
0251 clock-names = "top", "main", "pwm1";
0252 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
0253 assigned-clock-parents =
0254 <&topckgen CLK_TOP_UNIVPLL2_D4>;
0255 status = "disabled";
0256 };
0257
0258 i2c: i2c@11007000 {
0259 compatible = "mediatek,mt7629-i2c",
0260 "mediatek,mt2712-i2c";
0261 reg = <0x11007000 0x90>,
0262 <0x11000100 0x80>;
0263 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
0264 clock-div = <4>;
0265 clocks = <&pericfg CLK_PERI_I2C0_PD>,
0266 <&pericfg CLK_PERI_AP_DMA_PD>;
0267 clock-names = "main", "dma";
0268 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
0269 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
0270 #address-cells = <1>;
0271 #size-cells = <0>;
0272 status = "disabled";
0273 };
0274
0275 spi: spi@1100a000 {
0276 compatible = "mediatek,mt7629-spi",
0277 "mediatek,mt7622-spi";
0278 #address-cells = <1>;
0279 #size-cells = <0>;
0280 reg = <0x1100a000 0x100>;
0281 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
0282 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
0283 <&topckgen CLK_TOP_SPI0_SEL>,
0284 <&pericfg CLK_PERI_SPI0_PD>;
0285 clock-names = "parent-clk", "sel-clk", "spi-clk";
0286 status = "disabled";
0287 };
0288
0289 qspi: spi@11014000 {
0290 compatible = "mediatek,mt7629-nor",
0291 "mediatek,mt8173-nor";
0292 reg = <0x11014000 0xe0>;
0293 clocks = <&pericfg CLK_PERI_FLASH_PD>,
0294 <&topckgen CLK_TOP_FLASH_SEL>;
0295 clock-names = "spi", "sf";
0296 #address-cells = <1>;
0297 #size-cells = <0>;
0298 status = "disabled";
0299 };
0300
0301 ssusbsys: syscon@1a000000 {
0302 compatible = "mediatek,mt7629-ssusbsys", "syscon";
0303 reg = <0x1a000000 0x1000>;
0304 #clock-cells = <1>;
0305 #reset-cells = <1>;
0306 };
0307
0308 ssusb: usb@1a0c0000 {
0309 compatible = "mediatek,mt7629-xhci",
0310 "mediatek,mtk-xhci";
0311 reg = <0x1a0c0000 0x01000>,
0312 <0x1a0c3e00 0x0100>;
0313 reg-names = "mac", "ippc";
0314 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
0315 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
0316 <&ssusbsys CLK_SSUSB_REF_EN>,
0317 <&ssusbsys CLK_SSUSB_MCU_EN>,
0318 <&ssusbsys CLK_SSUSB_DMA_EN>;
0319 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
0320 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
0321 <&topckgen CLK_TOP_SATA_SEL>,
0322 <&topckgen CLK_TOP_HIF_SEL>;
0323 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
0324 <&topckgen CLK_TOP_UNIVPLL2_D4>,
0325 <&topckgen CLK_TOP_UNIVPLL1_D2>;
0326 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
0327 phys = <&u2port0 PHY_TYPE_USB2>,
0328 <&u3port0 PHY_TYPE_USB3>;
0329 status = "disabled";
0330 };
0331
0332 u3phy0: t-phy@1a0c4000 {
0333 compatible = "mediatek,mt7629-tphy",
0334 "mediatek,generic-tphy-v2";
0335 #address-cells = <1>;
0336 #size-cells = <1>;
0337 ranges = <0 0x1a0c4000 0xe00>;
0338 status = "disabled";
0339
0340 u2port0: usb-phy@0 {
0341 reg = <0 0x700>;
0342 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
0343 clock-names = "ref";
0344 #phy-cells = <1>;
0345 status = "okay";
0346 };
0347
0348 u3port0: usb-phy@700 {
0349 reg = <0x700 0x700>;
0350 clocks = <&clk20m>;
0351 clock-names = "ref";
0352 #phy-cells = <1>;
0353 status = "okay";
0354 };
0355 };
0356
0357 pciesys: syscon@1a100800 {
0358 compatible = "mediatek,mt7629-pciesys", "syscon";
0359 reg = <0x1a100800 0x1000>;
0360 #clock-cells = <1>;
0361 #reset-cells = <1>;
0362 };
0363
0364 pciecfg: pciecfg@1a140000 {
0365 compatible = "mediatek,generic-pciecfg", "syscon";
0366 reg = <0x1a140000 0x1000>;
0367 };
0368
0369 pcie1: pcie@1a145000 {
0370 compatible = "mediatek,mt7629-pcie";
0371 device_type = "pci";
0372 reg = <0x1a145000 0x1000>;
0373 reg-names = "port1";
0374 linux,pci-domain = <1>;
0375 #address-cells = <3>;
0376 #size-cells = <2>;
0377 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
0378 interrupt-names = "pcie_irq";
0379 clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
0380 <&pciesys CLK_PCIE_P0_AHB_EN>,
0381 <&pciesys CLK_PCIE_P1_AUX_EN>,
0382 <&pciesys CLK_PCIE_P1_AXI_EN>,
0383 <&pciesys CLK_PCIE_P1_OBFF_EN>,
0384 <&pciesys CLK_PCIE_P1_PIPE_EN>;
0385 clock-names = "sys_ck1", "ahb_ck1",
0386 "aux_ck1", "axi_ck1",
0387 "obff_ck1", "pipe_ck1";
0388 assigned-clocks = <&topckgen CLK_TOP_SATA_SEL>,
0389 <&topckgen CLK_TOP_AXI_SEL>,
0390 <&topckgen CLK_TOP_HIF_SEL>;
0391 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>,
0392 <&topckgen CLK_TOP_SYSPLL1_D2>,
0393 <&topckgen CLK_TOP_UNIVPLL1_D2>;
0394 phys = <&pcieport1 PHY_TYPE_PCIE>;
0395 phy-names = "pcie-phy1";
0396 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
0397 bus-range = <0x00 0xff>;
0398 ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
0399 status = "disabled";
0400
0401 #interrupt-cells = <1>;
0402 interrupt-map-mask = <0 0 0 7>;
0403 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
0404 <0 0 0 2 &pcie_intc1 1>,
0405 <0 0 0 3 &pcie_intc1 2>,
0406 <0 0 0 4 &pcie_intc1 3>;
0407 pcie_intc1: interrupt-controller {
0408 interrupt-controller;
0409 #address-cells = <0>;
0410 #interrupt-cells = <1>;
0411 };
0412 };
0413
0414 pciephy1: t-phy@1a14a000 {
0415 compatible = "mediatek,mt7629-tphy",
0416 "mediatek,generic-tphy-v2";
0417 #address-cells = <1>;
0418 #size-cells = <1>;
0419 ranges = <0 0x1a14a000 0x1000>;
0420 status = "disabled";
0421
0422 pcieport1: pcie-phy@0 {
0423 reg = <0 0x1000>;
0424 clocks = <&clk20m>;
0425 clock-names = "ref";
0426 #phy-cells = <1>;
0427 status = "okay";
0428 };
0429 };
0430
0431 ethsys: syscon@1b000000 {
0432 compatible = "mediatek,mt7629-ethsys", "syscon";
0433 reg = <0x1b000000 0x1000>;
0434 #clock-cells = <1>;
0435 #reset-cells = <1>;
0436 };
0437
0438 eth: ethernet@1b100000 {
0439 compatible = "mediatek,mt7629-eth","syscon";
0440 reg = <0x1b100000 0x20000>;
0441 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
0442 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
0443 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
0444 clocks = <&topckgen CLK_TOP_ETH_SEL>,
0445 <&topckgen CLK_TOP_F10M_REF_SEL>,
0446 <ðsys CLK_ETH_ESW_EN>,
0447 <ðsys CLK_ETH_GP0_EN>,
0448 <ðsys CLK_ETH_GP1_EN>,
0449 <ðsys CLK_ETH_GP2_EN>,
0450 <ðsys CLK_ETH_FE_EN>,
0451 <&sgmiisys0 CLK_SGMII_TX_EN>,
0452 <&sgmiisys0 CLK_SGMII_RX_EN>,
0453 <&sgmiisys0 CLK_SGMII_CDR_REF>,
0454 <&sgmiisys0 CLK_SGMII_CDR_FB>,
0455 <&sgmiisys1 CLK_SGMII_TX_EN>,
0456 <&sgmiisys1 CLK_SGMII_RX_EN>,
0457 <&sgmiisys1 CLK_SGMII_CDR_REF>,
0458 <&sgmiisys1 CLK_SGMII_CDR_FB>,
0459 <&apmixedsys CLK_APMIXED_SGMIPLL>,
0460 <&apmixedsys CLK_APMIXED_ETH2PLL>;
0461 clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1",
0462 "gp2", "fe", "sgmii_tx250m", "sgmii_rx250m",
0463 "sgmii_cdr_ref", "sgmii_cdr_fb",
0464 "sgmii2_tx250m", "sgmii2_rx250m",
0465 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
0466 "sgmii_ck", "eth2pll";
0467 assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
0468 <&topckgen CLK_TOP_F10M_REF_SEL>;
0469 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
0470 <&topckgen CLK_TOP_SGMIIPLL_D2>;
0471 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
0472 mediatek,ethsys = <ðsys>;
0473 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
0474 mediatek,infracfg = <&infracfg>;
0475 #address-cells = <1>;
0476 #size-cells = <0>;
0477 status = "disabled";
0478 };
0479
0480 sgmiisys0: syscon@1b128000 {
0481 compatible = "mediatek,mt7629-sgmiisys", "syscon";
0482 reg = <0x1b128000 0x3000>;
0483 #clock-cells = <1>;
0484 };
0485
0486 sgmiisys1: syscon@1b130000 {
0487 compatible = "mediatek,mt7629-sgmiisys", "syscon";
0488 reg = <0x1b130000 0x3000>;
0489 #clock-cells = <1>;
0490 };
0491 };
0492 };
