0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright © 2017-2020 MediaTek Inc.
0004 * Author: Sean Wang <sean.wang@mediatek.com>
0005 * Ryder Lee <ryder.lee@mediatek.com>
0006 *
0007 */
0008
0009 #include "mt7623.dtsi"
0010 #include <dt-bindings/memory/mt2701-larb-port.h>
0011
0012 / {
0013 aliases {
0014 rdma0 = &rdma0;
0015 rdma1 = &rdma1;
0016 };
0017
0018 g3dsys: syscon@13000000 {
0019 compatible = "mediatek,mt7623-g3dsys",
0020 "mediatek,mt2701-g3dsys",
0021 "syscon";
0022 reg = <0 0x13000000 0 0x200>;
0023 #clock-cells = <1>;
0024 #reset-cells = <1>;
0025 };
0026
0027 mali: gpu@13040000 {
0028 compatible = "mediatek,mt7623-mali", "arm,mali-450";
0029 reg = <0 0x13040000 0 0x30000>;
0030 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
0031 <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
0032 <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
0033 <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
0034 <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
0035 <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
0036 <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
0037 <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
0038 <GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>,
0039 <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>,
0040 <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
0041 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
0042 "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3",
0043 "pp";
0044 clocks = <&topckgen CLK_TOP_MMPLL>,
0045 <&g3dsys CLK_G3DSYS_CORE>;
0046 clock-names = "bus", "core";
0047 power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
0048 resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
0049 };
0050
0051 mmsys: syscon@14000000 {
0052 compatible = "mediatek,mt7623-mmsys",
0053 "mediatek,mt2701-mmsys",
0054 "syscon";
0055 reg = <0 0x14000000 0 0x1000>;
0056 #clock-cells = <1>;
0057 };
0058
0059 larb0: larb@14010000 {
0060 compatible = "mediatek,mt7623-smi-larb",
0061 "mediatek,mt2701-smi-larb";
0062 reg = <0 0x14010000 0 0x1000>;
0063 mediatek,smi = <&smi_common>;
0064 mediatek,larb-id = <0>;
0065 clocks = <&mmsys CLK_MM_SMI_LARB0>,
0066 <&mmsys CLK_MM_SMI_LARB0>;
0067 clock-names = "apb", "smi";
0068 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
0069 };
0070
0071 larb1: larb@16010000 {
0072 compatible = "mediatek,mt7623-smi-larb",
0073 "mediatek,mt2701-smi-larb";
0074 reg = <0 0x16010000 0 0x1000>;
0075 mediatek,smi = <&smi_common>;
0076 mediatek,larb-id = <1>;
0077 clocks = <&vdecsys CLK_VDEC_CKGEN>,
0078 <&vdecsys CLK_VDEC_LARB>;
0079 clock-names = "apb", "smi";
0080 power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
0081 };
0082
0083 larb2: larb@15001000 {
0084 compatible = "mediatek,mt7623-smi-larb",
0085 "mediatek,mt2701-smi-larb";
0086 reg = <0 0x15001000 0 0x1000>;
0087 mediatek,smi = <&smi_common>;
0088 mediatek,larb-id = <2>;
0089 clocks = <&imgsys CLK_IMG_SMI_COMM>,
0090 <&imgsys CLK_IMG_SMI_COMM>;
0091 clock-names = "apb", "smi";
0092 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
0093 };
0094
0095 imgsys: syscon@15000000 {
0096 compatible = "mediatek,mt7623-imgsys",
0097 "mediatek,mt2701-imgsys",
0098 "syscon";
0099 reg = <0 0x15000000 0 0x1000>;
0100 #clock-cells = <1>;
0101 };
0102
0103 iommu: mmsys_iommu@10205000 {
0104 compatible = "mediatek,mt7623-m4u",
0105 "mediatek,mt2701-m4u";
0106 reg = <0 0x10205000 0 0x1000>;
0107 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
0108 clocks = <&infracfg CLK_INFRA_M4U>;
0109 clock-names = "bclk";
0110 mediatek,larbs = <&larb0 &larb1 &larb2>;
0111 #iommu-cells = <1>;
0112 };
0113
0114 jpegdec: jpegdec@15004000 {
0115 compatible = "mediatek,mt7623-jpgdec",
0116 "mediatek,mt2701-jpgdec";
0117 reg = <0 0x15004000 0 0x1000>;
0118 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
0119 clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
0120 <&imgsys CLK_IMG_JPGDEC>;
0121 clock-names = "jpgdec-smi",
0122 "jpgdec";
0123 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
0124 iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
0125 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
0126 };
0127
0128 smi_common: smi@1000c000 {
0129 compatible = "mediatek,mt7623-smi-common",
0130 "mediatek,mt2701-smi-common";
0131 reg = <0 0x1000c000 0 0x1000>;
0132 clocks = <&infracfg CLK_INFRA_SMI>,
0133 <&mmsys CLK_MM_SMI_COMMON>,
0134 <&infracfg CLK_INFRA_SMI>;
0135 clock-names = "apb", "smi", "async";
0136 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
0137 };
0138
0139 ovl: ovl@14007000 {
0140 compatible = "mediatek,mt7623-disp-ovl",
0141 "mediatek,mt2701-disp-ovl";
0142 reg = <0 0x14007000 0 0x1000>;
0143 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
0144 clocks = <&mmsys CLK_MM_DISP_OVL>;
0145 iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
0146 };
0147
0148 rdma0: rdma@14008000 {
0149 compatible = "mediatek,mt7623-disp-rdma",
0150 "mediatek,mt2701-disp-rdma";
0151 reg = <0 0x14008000 0 0x1000>;
0152 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
0153 clocks = <&mmsys CLK_MM_DISP_RDMA>;
0154 iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
0155 };
0156
0157 wdma@14009000 {
0158 compatible = "mediatek,mt7623-disp-wdma",
0159 "mediatek,mt2701-disp-wdma";
0160 reg = <0 0x14009000 0 0x1000>;
0161 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
0162 clocks = <&mmsys CLK_MM_DISP_WDMA>;
0163 iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
0164 };
0165
0166 bls: pwm@1400a000 {
0167 compatible = "mediatek,mt7623-disp-pwm",
0168 "mediatek,mt2701-disp-pwm";
0169 reg = <0 0x1400a000 0 0x1000>;
0170 #pwm-cells = <2>;
0171 clocks = <&mmsys CLK_MM_MDP_BLS_26M>,
0172 <&mmsys CLK_MM_DISP_BLS>;
0173 clock-names = "main", "mm";
0174 status = "disabled";
0175 };
0176
0177 color: color@1400b000 {
0178 compatible = "mediatek,mt7623-disp-color",
0179 "mediatek,mt2701-disp-color";
0180 reg = <0 0x1400b000 0 0x1000>;
0181 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
0182 clocks = <&mmsys CLK_MM_DISP_COLOR>;
0183 };
0184
0185 dsi: dsi@1400c000 {
0186 compatible = "mediatek,mt7623-dsi",
0187 "mediatek,mt2701-dsi";
0188 reg = <0 0x1400c000 0 0x1000>;
0189 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
0190 clocks = <&mmsys CLK_MM_DSI_ENGINE>,
0191 <&mmsys CLK_MM_DSI_DIG>,
0192 <&mipi_tx0>;
0193 clock-names = "engine", "digital", "hs";
0194 phys = <&mipi_tx0>;
0195 phy-names = "dphy";
0196 status = "disabled";
0197 };
0198
0199 mutex: mutex@1400e000 {
0200 compatible = "mediatek,mt7623-disp-mutex",
0201 "mediatek,mt2701-disp-mutex";
0202 reg = <0 0x1400e000 0 0x1000>;
0203 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
0204 clocks = <&mmsys CLK_MM_MUTEX_32K>;
0205 };
0206
0207 rdma1: rdma@14012000 {
0208 compatible = "mediatek,mt7623-disp-rdma",
0209 "mediatek,mt2701-disp-rdma";
0210 reg = <0 0x14012000 0 0x1000>;
0211 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
0212 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
0213 iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
0214 };
0215
0216 dpi0: dpi@14014000 {
0217 compatible = "mediatek,mt7623-dpi",
0218 "mediatek,mt2701-dpi";
0219 reg = <0 0x14014000 0 0x1000>;
0220 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
0221 clocks = <&mmsys CLK_MM_DPI1_DIGL>,
0222 <&mmsys CLK_MM_DPI1_ENGINE>,
0223 <&apmixedsys CLK_APMIXED_TVDPLL>;
0224 clock-names = "pixel", "engine", "pll";
0225 status = "disabled";
0226 };
0227
0228 hdmi0: hdmi@14015000 {
0229 compatible = "mediatek,mt7623-hdmi",
0230 "mediatek,mt2701-hdmi";
0231 reg = <0 0x14015000 0 0x400>;
0232 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
0233 <&mmsys CLK_MM_HDMI_PLL>,
0234 <&mmsys CLK_MM_HDMI_AUDIO>,
0235 <&mmsys CLK_MM_HDMI_SPDIF>;
0236 clock-names = "pixel", "pll", "bclk", "spdif";
0237 phys = <&hdmi_phy>;
0238 phy-names = "hdmi";
0239 mediatek,syscon-hdmi = <&mmsys 0x900>;
0240 cec = <&cec>;
0241 status = "disabled";
0242 };
0243
0244 mipi_tx0: dsi-phy@10010000 {
0245 compatible = "mediatek,mt7623-mipi-tx",
0246 "mediatek,mt2701-mipi-tx";
0247 reg = <0 0x10010000 0 0x90>;
0248 clocks = <&clk26m>;
0249 clock-output-names = "mipi_tx0_pll";
0250 #clock-cells = <0>;
0251 #phy-cells = <0>;
0252 };
0253
0254 cec: cec@10012000 {
0255 compatible = "mediatek,mt7623-cec",
0256 "mediatek,mt8173-cec";
0257 reg = <0 0x10012000 0 0xbc>;
0258 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
0259 clocks = <&infracfg CLK_INFRA_CEC>;
0260 status = "disabled";
0261 };
0262
0263 hdmi_phy: hdmi-phy@10209100 {
0264 compatible = "mediatek,mt7623-hdmi-phy",
0265 "mediatek,mt2701-hdmi-phy";
0266 reg = <0 0x10209100 0 0x24>;
0267 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
0268 clock-names = "pll_ref";
0269 clock-output-names = "hdmitx_dig_cts";
0270 #clock-cells = <0>;
0271 #phy-cells = <0>;
0272 status = "disabled";
0273 };
0274
0275 hdmiddc0: i2c@11013000 {
0276 compatible = "mediatek,mt7623-hdmi-ddc",
0277 "mediatek,mt8173-hdmi-ddc";
0278 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
0279 reg = <0 0x11013000 0 0x1C>;
0280 clocks = <&pericfg CLK_PERI_I2C3>;
0281 clock-names = "ddc-i2c";
0282 status = "disabled";
0283 };
0284 };
0285
0286 &pio {
0287 hdmi_pins_a: hdmi-default {
0288 pins-hdmi {
0289 pinmux = <MT7623_PIN_123_HTPLG_FUNC_HTPLG>;
0290 input-enable;
0291 bias-pull-down;
0292 };
0293 };
0294
0295 hdmi_ddc_pins_a: hdmi_ddc-default {
0296 pins-hdmi-ddc {
0297 pinmux = <MT7623_PIN_124_GPIO124_FUNC_HDMISCK>,
0298 <MT7623_PIN_125_GPIO125_FUNC_HDMISD>;
0299 };
0300 };
0301 };
