0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (c) 2017-2018 MediaTek Inc.
0004 * Author: John Crispin <john@phrozen.org>
0005 * Sean Wang <sean.wang@mediatek.com>
0006 * Ryder Lee <ryder.lee@mediatek.com>
0007 *
0008 */
0009
0010 #include <dt-bindings/interrupt-controller/irq.h>
0011 #include <dt-bindings/interrupt-controller/arm-gic.h>
0012 #include <dt-bindings/clock/mt2701-clk.h>
0013 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
0014 #include <dt-bindings/power/mt2701-power.h>
0015 #include <dt-bindings/gpio/gpio.h>
0016 #include <dt-bindings/phy/phy.h>
0017 #include <dt-bindings/reset/mt2701-resets.h>
0018 #include <dt-bindings/thermal/thermal.h>
0019
0020 / {
0021 compatible = "mediatek,mt7623";
0022 interrupt-parent = <&sysirq>;
0023 #address-cells = <2>;
0024 #size-cells = <2>;
0025
0026 cpu_opp_table: opp-table {
0027 compatible = "operating-points-v2";
0028 opp-shared;
0029
0030 opp-98000000 {
0031 opp-hz = /bits/ 64 <98000000>;
0032 opp-microvolt = <1050000>;
0033 };
0034
0035 opp-198000000 {
0036 opp-hz = /bits/ 64 <198000000>;
0037 opp-microvolt = <1050000>;
0038 };
0039
0040 opp-398000000 {
0041 opp-hz = /bits/ 64 <398000000>;
0042 opp-microvolt = <1050000>;
0043 };
0044
0045 opp-598000000 {
0046 opp-hz = /bits/ 64 <598000000>;
0047 opp-microvolt = <1050000>;
0048 };
0049
0050 opp-747500000 {
0051 opp-hz = /bits/ 64 <747500000>;
0052 opp-microvolt = <1050000>;
0053 };
0054
0055 opp-1040000000 {
0056 opp-hz = /bits/ 64 <1040000000>;
0057 opp-microvolt = <1150000>;
0058 };
0059
0060 opp-1196000000 {
0061 opp-hz = /bits/ 64 <1196000000>;
0062 opp-microvolt = <1200000>;
0063 };
0064
0065 opp-1300000000 {
0066 opp-hz = /bits/ 64 <1300000000>;
0067 opp-microvolt = <1300000>;
0068 };
0069 };
0070
0071 cpus {
0072 #address-cells = <1>;
0073 #size-cells = <0>;
0074 enable-method = "mediatek,mt6589-smp";
0075
0076 cpu0: cpu@0 {
0077 device_type = "cpu";
0078 compatible = "arm,cortex-a7";
0079 reg = <0x0>;
0080 clocks = <&infracfg CLK_INFRA_CPUSEL>,
0081 <&apmixedsys CLK_APMIXED_MAINPLL>;
0082 clock-names = "cpu", "intermediate";
0083 operating-points-v2 = <&cpu_opp_table>;
0084 #cooling-cells = <2>;
0085 clock-frequency = <1300000000>;
0086 };
0087
0088 cpu1: cpu@1 {
0089 device_type = "cpu";
0090 compatible = "arm,cortex-a7";
0091 reg = <0x1>;
0092 clocks = <&infracfg CLK_INFRA_CPUSEL>,
0093 <&apmixedsys CLK_APMIXED_MAINPLL>;
0094 clock-names = "cpu", "intermediate";
0095 operating-points-v2 = <&cpu_opp_table>;
0096 #cooling-cells = <2>;
0097 clock-frequency = <1300000000>;
0098 };
0099
0100 cpu2: cpu@2 {
0101 device_type = "cpu";
0102 compatible = "arm,cortex-a7";
0103 reg = <0x2>;
0104 clocks = <&infracfg CLK_INFRA_CPUSEL>,
0105 <&apmixedsys CLK_APMIXED_MAINPLL>;
0106 clock-names = "cpu", "intermediate";
0107 operating-points-v2 = <&cpu_opp_table>;
0108 #cooling-cells = <2>;
0109 clock-frequency = <1300000000>;
0110 };
0111
0112 cpu3: cpu@3 {
0113 device_type = "cpu";
0114 compatible = "arm,cortex-a7";
0115 reg = <0x3>;
0116 clocks = <&infracfg CLK_INFRA_CPUSEL>,
0117 <&apmixedsys CLK_APMIXED_MAINPLL>;
0118 clock-names = "cpu", "intermediate";
0119 operating-points-v2 = <&cpu_opp_table>;
0120 #cooling-cells = <2>;
0121 clock-frequency = <1300000000>;
0122 };
0123 };
0124
0125 pmu {
0126 compatible = "arm,cortex-a7-pmu";
0127 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>,
0128 <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>,
0129 <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>,
0130 <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
0131 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0132 };
0133
0134 system_clk: dummy13m {
0135 compatible = "fixed-clock";
0136 clock-frequency = <13000000>;
0137 #clock-cells = <0>;
0138 };
0139
0140 rtc32k: oscillator-1 {
0141 compatible = "fixed-clock";
0142 #clock-cells = <0>;
0143 clock-frequency = <32000>;
0144 clock-output-names = "rtc32k";
0145 };
0146
0147 clk26m: oscillator-0 {
0148 compatible = "fixed-clock";
0149 #clock-cells = <0>;
0150 clock-frequency = <26000000>;
0151 clock-output-names = "clk26m";
0152 };
0153
0154 thermal-zones {
0155 cpu_thermal: cpu-thermal {
0156 polling-delay-passive = <1000>;
0157 polling-delay = <1000>;
0158
0159 thermal-sensors = <&thermal 0>;
0160
0161 trips {
0162 cpu_passive: cpu-passive {
0163 temperature = <57000>;
0164 hysteresis = <2000>;
0165 type = "passive";
0166 };
0167
0168 cpu_active: cpu-active {
0169 temperature = <67000>;
0170 hysteresis = <2000>;
0171 type = "active";
0172 };
0173
0174 cpu_hot: cpu-hot {
0175 temperature = <87000>;
0176 hysteresis = <2000>;
0177 type = "hot";
0178 };
0179
0180 cpu-crit {
0181 temperature = <107000>;
0182 hysteresis = <2000>;
0183 type = "critical";
0184 };
0185 };
0186
0187 cooling-maps {
0188 map0 {
0189 trip = <&cpu_passive>;
0190 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0191 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0192 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0193 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0194 };
0195
0196 map1 {
0197 trip = <&cpu_active>;
0198 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0199 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0200 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0201 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0202 };
0203
0204 map2 {
0205 trip = <&cpu_hot>;
0206 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0207 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0208 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0209 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0210 };
0211 };
0212 };
0213 };
0214
0215 timer {
0216 compatible = "arm,armv7-timer";
0217 interrupt-parent = <&gic>;
0218 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0219 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0220 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0221 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0222 clock-frequency = <13000000>;
0223 arm,cpu-registers-not-fw-configured;
0224 };
0225
0226 topckgen: syscon@10000000 {
0227 compatible = "mediatek,mt7623-topckgen",
0228 "mediatek,mt2701-topckgen",
0229 "syscon";
0230 reg = <0 0x10000000 0 0x1000>;
0231 #clock-cells = <1>;
0232 };
0233
0234 infracfg: syscon@10001000 {
0235 compatible = "mediatek,mt7623-infracfg",
0236 "mediatek,mt2701-infracfg",
0237 "syscon";
0238 reg = <0 0x10001000 0 0x1000>;
0239 #clock-cells = <1>;
0240 #reset-cells = <1>;
0241 };
0242
0243 pericfg: syscon@10003000 {
0244 compatible = "mediatek,mt7623-pericfg",
0245 "mediatek,mt2701-pericfg",
0246 "syscon";
0247 reg = <0 0x10003000 0 0x1000>;
0248 #clock-cells = <1>;
0249 #reset-cells = <1>;
0250 };
0251
0252 pio: pinctrl@10005000 {
0253 compatible = "mediatek,mt7623-pinctrl";
0254 reg = <0 0x1000b000 0 0x1000>;
0255 mediatek,pctl-regmap = <&syscfg_pctl_a>;
0256 pins-are-numbered;
0257 gpio-controller;
0258 #gpio-cells = <2>;
0259 interrupt-controller;
0260 interrupt-parent = <&gic>;
0261 #interrupt-cells = <2>;
0262 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
0263 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0264 };
0265
0266 syscfg_pctl_a: syscfg@10005000 {
0267 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
0268 reg = <0 0x10005000 0 0x1000>;
0269 };
0270
0271 scpsys: power-controller@10006000 {
0272 compatible = "mediatek,mt7623-scpsys",
0273 "mediatek,mt2701-scpsys",
0274 "syscon";
0275 #power-domain-cells = <1>;
0276 reg = <0 0x10006000 0 0x1000>;
0277 infracfg = <&infracfg>;
0278 clocks = <&topckgen CLK_TOP_MM_SEL>,
0279 <&topckgen CLK_TOP_MFG_SEL>,
0280 <&topckgen CLK_TOP_ETHIF_SEL>;
0281 clock-names = "mm", "mfg", "ethif";
0282 };
0283
0284 watchdog: watchdog@10007000 {
0285 compatible = "mediatek,mt7623-wdt",
0286 "mediatek,mt6589-wdt";
0287 reg = <0 0x10007000 0 0x100>;
0288 };
0289
0290 timer: timer@10008000 {
0291 compatible = "mediatek,mt7623-timer",
0292 "mediatek,mt6577-timer";
0293 reg = <0 0x10008000 0 0x80>;
0294 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
0295 clocks = <&system_clk>, <&rtc32k>;
0296 clock-names = "system-clk", "rtc-clk";
0297 };
0298
0299 pwrap: pwrap@1000d000 {
0300 compatible = "mediatek,mt7623-pwrap",
0301 "mediatek,mt2701-pwrap";
0302 reg = <0 0x1000d000 0 0x1000>;
0303 reg-names = "pwrap";
0304 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
0305 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
0306 reset-names = "pwrap";
0307 clocks = <&infracfg CLK_INFRA_PMICSPI>,
0308 <&infracfg CLK_INFRA_PMICWRAP>;
0309 clock-names = "spi", "wrap";
0310 };
0311
0312 cir: cir@10013000 {
0313 compatible = "mediatek,mt7623-cir";
0314 reg = <0 0x10013000 0 0x1000>;
0315 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
0316 clocks = <&infracfg CLK_INFRA_IRRX>;
0317 clock-names = "clk";
0318 status = "disabled";
0319 };
0320
0321 sysirq: interrupt-controller@10200100 {
0322 compatible = "mediatek,mt7623-sysirq",
0323 "mediatek,mt6577-sysirq";
0324 interrupt-controller;
0325 #interrupt-cells = <3>;
0326 interrupt-parent = <&gic>;
0327 reg = <0 0x10200100 0 0x1c>;
0328 };
0329
0330 efuse: efuse@10206000 {
0331 compatible = "mediatek,mt7623-efuse",
0332 "mediatek,mt8173-efuse";
0333 reg = <0 0x10206000 0 0x1000>;
0334 #address-cells = <1>;
0335 #size-cells = <1>;
0336 thermal_calibration_data: calib@424 {
0337 reg = <0x424 0xc>;
0338 };
0339 };
0340
0341 apmixedsys: syscon@10209000 {
0342 compatible = "mediatek,mt7623-apmixedsys",
0343 "mediatek,mt2701-apmixedsys",
0344 "syscon";
0345 reg = <0 0x10209000 0 0x1000>;
0346 #clock-cells = <1>;
0347 };
0348
0349 rng: rng@1020f000 {
0350 compatible = "mediatek,mt7623-rng";
0351 reg = <0 0x1020f000 0 0x1000>;
0352 clocks = <&infracfg CLK_INFRA_TRNG>;
0353 clock-names = "rng";
0354 };
0355
0356 gic: interrupt-controller@10211000 {
0357 compatible = "arm,cortex-a7-gic";
0358 interrupt-controller;
0359 #interrupt-cells = <3>;
0360 interrupt-parent = <&gic>;
0361 reg = <0 0x10211000 0 0x1000>,
0362 <0 0x10212000 0 0x2000>,
0363 <0 0x10214000 0 0x2000>,
0364 <0 0x10216000 0 0x2000>;
0365 };
0366
0367 auxadc: adc@11001000 {
0368 compatible = "mediatek,mt7623-auxadc",
0369 "mediatek,mt2701-auxadc";
0370 reg = <0 0x11001000 0 0x1000>;
0371 clocks = <&pericfg CLK_PERI_AUXADC>;
0372 clock-names = "main";
0373 #io-channel-cells = <1>;
0374 };
0375
0376 uart0: serial@11002000 {
0377 compatible = "mediatek,mt7623-uart",
0378 "mediatek,mt6577-uart";
0379 reg = <0 0x11002000 0 0x400>;
0380 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
0381 clocks = <&pericfg CLK_PERI_UART0_SEL>,
0382 <&pericfg CLK_PERI_UART0>;
0383 clock-names = "baud", "bus";
0384 status = "disabled";
0385 };
0386
0387 uart1: serial@11003000 {
0388 compatible = "mediatek,mt7623-uart",
0389 "mediatek,mt6577-uart";
0390 reg = <0 0x11003000 0 0x400>;
0391 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
0392 clocks = <&pericfg CLK_PERI_UART1_SEL>,
0393 <&pericfg CLK_PERI_UART1>;
0394 clock-names = "baud", "bus";
0395 status = "disabled";
0396 };
0397
0398 uart2: serial@11004000 {
0399 compatible = "mediatek,mt7623-uart",
0400 "mediatek,mt6577-uart";
0401 reg = <0 0x11004000 0 0x400>;
0402 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
0403 clocks = <&pericfg CLK_PERI_UART2_SEL>,
0404 <&pericfg CLK_PERI_UART2>;
0405 clock-names = "baud", "bus";
0406 status = "disabled";
0407 };
0408
0409 uart3: serial@11005000 {
0410 compatible = "mediatek,mt7623-uart",
0411 "mediatek,mt6577-uart";
0412 reg = <0 0x11005000 0 0x400>;
0413 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
0414 clocks = <&pericfg CLK_PERI_UART3_SEL>,
0415 <&pericfg CLK_PERI_UART3>;
0416 clock-names = "baud", "bus";
0417 status = "disabled";
0418 };
0419
0420 pwm: pwm@11006000 {
0421 compatible = "mediatek,mt7623-pwm";
0422 reg = <0 0x11006000 0 0x1000>;
0423 #pwm-cells = <2>;
0424 clocks = <&topckgen CLK_TOP_PWM_SEL>,
0425 <&pericfg CLK_PERI_PWM>,
0426 <&pericfg CLK_PERI_PWM1>,
0427 <&pericfg CLK_PERI_PWM2>,
0428 <&pericfg CLK_PERI_PWM3>,
0429 <&pericfg CLK_PERI_PWM4>,
0430 <&pericfg CLK_PERI_PWM5>;
0431 clock-names = "top", "main", "pwm1", "pwm2",
0432 "pwm3", "pwm4", "pwm5";
0433 status = "disabled";
0434 };
0435
0436 i2c0: i2c@11007000 {
0437 compatible = "mediatek,mt7623-i2c",
0438 "mediatek,mt6577-i2c";
0439 reg = <0 0x11007000 0 0x70>,
0440 <0 0x11000200 0 0x80>;
0441 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
0442 clock-div = <16>;
0443 clocks = <&pericfg CLK_PERI_I2C0>,
0444 <&pericfg CLK_PERI_AP_DMA>;
0445 clock-names = "main", "dma";
0446 #address-cells = <1>;
0447 #size-cells = <0>;
0448 status = "disabled";
0449 };
0450
0451 i2c1: i2c@11008000 {
0452 compatible = "mediatek,mt7623-i2c",
0453 "mediatek,mt6577-i2c";
0454 reg = <0 0x11008000 0 0x70>,
0455 <0 0x11000280 0 0x80>;
0456 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
0457 clock-div = <16>;
0458 clocks = <&pericfg CLK_PERI_I2C1>,
0459 <&pericfg CLK_PERI_AP_DMA>;
0460 clock-names = "main", "dma";
0461 #address-cells = <1>;
0462 #size-cells = <0>;
0463 status = "disabled";
0464 };
0465
0466 i2c2: i2c@11009000 {
0467 compatible = "mediatek,mt7623-i2c",
0468 "mediatek,mt6577-i2c";
0469 reg = <0 0x11009000 0 0x70>,
0470 <0 0x11000300 0 0x80>;
0471 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
0472 clock-div = <16>;
0473 clocks = <&pericfg CLK_PERI_I2C2>,
0474 <&pericfg CLK_PERI_AP_DMA>;
0475 clock-names = "main", "dma";
0476 #address-cells = <1>;
0477 #size-cells = <0>;
0478 status = "disabled";
0479 };
0480
0481 spi0: spi@1100a000 {
0482 compatible = "mediatek,mt7623-spi",
0483 "mediatek,mt2701-spi";
0484 #address-cells = <1>;
0485 #size-cells = <0>;
0486 reg = <0 0x1100a000 0 0x100>;
0487 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
0488 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
0489 <&topckgen CLK_TOP_SPI0_SEL>,
0490 <&pericfg CLK_PERI_SPI0>;
0491 clock-names = "parent-clk", "sel-clk", "spi-clk";
0492 status = "disabled";
0493 };
0494
0495 thermal: thermal@1100b000 {
0496 #thermal-sensor-cells = <1>;
0497 compatible = "mediatek,mt7623-thermal",
0498 "mediatek,mt2701-thermal";
0499 reg = <0 0x1100b000 0 0x1000>;
0500 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
0501 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
0502 clock-names = "therm", "auxadc";
0503 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
0504 reset-names = "therm";
0505 mediatek,auxadc = <&auxadc>;
0506 mediatek,apmixedsys = <&apmixedsys>;
0507 nvmem-cells = <&thermal_calibration_data>;
0508 nvmem-cell-names = "calibration-data";
0509 };
0510
0511 btif: serial@1100c000 {
0512 compatible = "mediatek,mt7623-btif",
0513 "mediatek,mtk-btif";
0514 reg = <0 0x1100c000 0 0x1000>;
0515 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>;
0516 clocks = <&pericfg CLK_PERI_BTIF>;
0517 clock-names = "main";
0518 reg-shift = <2>;
0519 reg-io-width = <4>;
0520 status = "disabled";
0521 };
0522
0523 nandc: nfi@1100d000 {
0524 compatible = "mediatek,mt7623-nfc",
0525 "mediatek,mt2701-nfc";
0526 reg = <0 0x1100d000 0 0x1000>;
0527 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
0528 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
0529 clocks = <&pericfg CLK_PERI_NFI>,
0530 <&pericfg CLK_PERI_NFI_PAD>;
0531 clock-names = "nfi_clk", "pad_clk";
0532 status = "disabled";
0533 ecc-engine = <&bch>;
0534 #address-cells = <1>;
0535 #size-cells = <0>;
0536 };
0537
0538 bch: ecc@1100e000 {
0539 compatible = "mediatek,mt7623-ecc",
0540 "mediatek,mt2701-ecc";
0541 reg = <0 0x1100e000 0 0x1000>;
0542 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
0543 clocks = <&pericfg CLK_PERI_NFI_ECC>;
0544 clock-names = "nfiecc_clk";
0545 status = "disabled";
0546 };
0547
0548 nor_flash: spi@11014000 {
0549 compatible = "mediatek,mt7623-nor",
0550 "mediatek,mt8173-nor";
0551 reg = <0 0x11014000 0 0x1000>;
0552 clocks = <&pericfg CLK_PERI_FLASH>,
0553 <&topckgen CLK_TOP_FLASH_SEL>;
0554 clock-names = "spi", "sf";
0555 #address-cells = <1>;
0556 #size-cells = <0>;
0557 status = "disabled";
0558 };
0559
0560 spi1: spi@11016000 {
0561 compatible = "mediatek,mt7623-spi",
0562 "mediatek,mt2701-spi";
0563 #address-cells = <1>;
0564 #size-cells = <0>;
0565 reg = <0 0x11016000 0 0x100>;
0566 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
0567 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
0568 <&topckgen CLK_TOP_SPI1_SEL>,
0569 <&pericfg CLK_PERI_SPI1>;
0570 clock-names = "parent-clk", "sel-clk", "spi-clk";
0571 status = "disabled";
0572 };
0573
0574 spi2: spi@11017000 {
0575 compatible = "mediatek,mt7623-spi",
0576 "mediatek,mt2701-spi";
0577 #address-cells = <1>;
0578 #size-cells = <0>;
0579 reg = <0 0x11017000 0 0x1000>;
0580 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
0581 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
0582 <&topckgen CLK_TOP_SPI2_SEL>,
0583 <&pericfg CLK_PERI_SPI2>;
0584 clock-names = "parent-clk", "sel-clk", "spi-clk";
0585 status = "disabled";
0586 };
0587
0588 usb0: usb@11200000 {
0589 compatible = "mediatek,mt7623-musb",
0590 "mediatek,mtk-musb";
0591 reg = <0 0x11200000 0 0x1000>;
0592 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
0593 interrupt-names = "mc";
0594 phys = <&u2port2 PHY_TYPE_USB2>;
0595 dr_mode = "otg";
0596 clocks = <&pericfg CLK_PERI_USB0>,
0597 <&pericfg CLK_PERI_USB0_MCU>,
0598 <&pericfg CLK_PERI_USB_SLV>;
0599 clock-names = "main","mcu","univpll";
0600 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
0601 status = "disabled";
0602 };
0603
0604 u2phy1: t-phy@11210000 {
0605 compatible = "mediatek,mt7623-tphy",
0606 "mediatek,generic-tphy-v1";
0607 reg = <0 0x11210000 0 0x0800>;
0608 #address-cells = <2>;
0609 #size-cells = <2>;
0610 ranges;
0611 status = "disabled";
0612
0613 u2port2: usb-phy@11210800 {
0614 reg = <0 0x11210800 0 0x0100>;
0615 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
0616 clock-names = "ref";
0617 #phy-cells = <1>;
0618 };
0619 };
0620
0621 audsys: clock-controller@11220000 {
0622 compatible = "mediatek,mt7623-audsys",
0623 "mediatek,mt2701-audsys",
0624 "syscon";
0625 reg = <0 0x11220000 0 0x2000>;
0626 #clock-cells = <1>;
0627
0628 afe: audio-controller {
0629 compatible = "mediatek,mt7623-audio",
0630 "mediatek,mt2701-audio";
0631 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
0632 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
0633 interrupt-names = "afe", "asys";
0634 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
0635
0636 clocks = <&infracfg CLK_INFRA_AUDIO>,
0637 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
0638 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
0639 <&topckgen CLK_TOP_AUD_48K_TIMING>,
0640 <&topckgen CLK_TOP_AUD_44K_TIMING>,
0641 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
0642 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
0643 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
0644 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
0645 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
0646 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
0647 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
0648 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
0649 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
0650 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
0651 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
0652 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
0653 <&audsys CLK_AUD_I2SO1>,
0654 <&audsys CLK_AUD_I2SO2>,
0655 <&audsys CLK_AUD_I2SO3>,
0656 <&audsys CLK_AUD_I2SO4>,
0657 <&audsys CLK_AUD_I2SIN1>,
0658 <&audsys CLK_AUD_I2SIN2>,
0659 <&audsys CLK_AUD_I2SIN3>,
0660 <&audsys CLK_AUD_I2SIN4>,
0661 <&audsys CLK_AUD_ASRCO1>,
0662 <&audsys CLK_AUD_ASRCO2>,
0663 <&audsys CLK_AUD_ASRCO3>,
0664 <&audsys CLK_AUD_ASRCO4>,
0665 <&audsys CLK_AUD_AFE>,
0666 <&audsys CLK_AUD_AFE_CONN>,
0667 <&audsys CLK_AUD_A1SYS>,
0668 <&audsys CLK_AUD_A2SYS>,
0669 <&audsys CLK_AUD_AFE_MRGIF>;
0670
0671 clock-names = "infra_sys_audio_clk",
0672 "top_audio_mux1_sel",
0673 "top_audio_mux2_sel",
0674 "top_audio_a1sys_hp",
0675 "top_audio_a2sys_hp",
0676 "i2s0_src_sel",
0677 "i2s1_src_sel",
0678 "i2s2_src_sel",
0679 "i2s3_src_sel",
0680 "i2s0_src_div",
0681 "i2s1_src_div",
0682 "i2s2_src_div",
0683 "i2s3_src_div",
0684 "i2s0_mclk_en",
0685 "i2s1_mclk_en",
0686 "i2s2_mclk_en",
0687 "i2s3_mclk_en",
0688 "i2so0_hop_ck",
0689 "i2so1_hop_ck",
0690 "i2so2_hop_ck",
0691 "i2so3_hop_ck",
0692 "i2si0_hop_ck",
0693 "i2si1_hop_ck",
0694 "i2si2_hop_ck",
0695 "i2si3_hop_ck",
0696 "asrc0_out_ck",
0697 "asrc1_out_ck",
0698 "asrc2_out_ck",
0699 "asrc3_out_ck",
0700 "audio_afe_pd",
0701 "audio_afe_conn_pd",
0702 "audio_a1sys_pd",
0703 "audio_a2sys_pd",
0704 "audio_mrgif_pd";
0705
0706 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
0707 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
0708 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
0709 <&topckgen CLK_TOP_AUD_MUX2_DIV>;
0710 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
0711 <&topckgen CLK_TOP_AUD2PLL_90M>;
0712 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
0713 };
0714 };
0715
0716 mmc0: mmc@11230000 {
0717 compatible = "mediatek,mt7623-mmc",
0718 "mediatek,mt2701-mmc";
0719 reg = <0 0x11230000 0 0x1000>;
0720 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
0721 clocks = <&pericfg CLK_PERI_MSDC30_0>,
0722 <&topckgen CLK_TOP_MSDC30_0_SEL>;
0723 clock-names = "source", "hclk";
0724 status = "disabled";
0725 };
0726
0727 mmc1: mmc@11240000 {
0728 compatible = "mediatek,mt7623-mmc",
0729 "mediatek,mt2701-mmc";
0730 reg = <0 0x11240000 0 0x1000>;
0731 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
0732 clocks = <&pericfg CLK_PERI_MSDC30_1>,
0733 <&topckgen CLK_TOP_MSDC30_1_SEL>;
0734 clock-names = "source", "hclk";
0735 status = "disabled";
0736 };
0737
0738 vdecsys: syscon@16000000 {
0739 compatible = "mediatek,mt7623-vdecsys",
0740 "mediatek,mt2701-vdecsys",
0741 "syscon";
0742 reg = <0 0x16000000 0 0x1000>;
0743 #clock-cells = <1>;
0744 };
0745
0746 hifsys: syscon@1a000000 {
0747 compatible = "mediatek,mt7623-hifsys",
0748 "mediatek,mt2701-hifsys",
0749 "syscon";
0750 reg = <0 0x1a000000 0 0x1000>;
0751 #clock-cells = <1>;
0752 #reset-cells = <1>;
0753 };
0754
0755 pcie: pcie@1a140000 {
0756 compatible = "mediatek,mt7623-pcie";
0757 device_type = "pci";
0758 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
0759 <0 0x1a142000 0 0x1000>, /* Port0 registers */
0760 <0 0x1a143000 0 0x1000>, /* Port1 registers */
0761 <0 0x1a144000 0 0x1000>; /* Port2 registers */
0762 reg-names = "subsys", "port0", "port1", "port2";
0763 #address-cells = <3>;
0764 #size-cells = <2>;
0765 #interrupt-cells = <1>;
0766 interrupt-map-mask = <0xf800 0 0 0>;
0767 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
0768 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
0769 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
0770 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
0771 <&hifsys CLK_HIFSYS_PCIE0>,
0772 <&hifsys CLK_HIFSYS_PCIE1>,
0773 <&hifsys CLK_HIFSYS_PCIE2>;
0774 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
0775 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
0776 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
0777 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
0778 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
0779 phys = <&pcie0_port PHY_TYPE_PCIE>,
0780 <&pcie1_port PHY_TYPE_PCIE>,
0781 <&u3port1 PHY_TYPE_PCIE>;
0782 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
0783 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
0784 bus-range = <0x00 0xff>;
0785 status = "disabled";
0786 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
0787 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
0788
0789 pcie@0,0 {
0790 reg = <0x0000 0 0 0 0>;
0791 #address-cells = <3>;
0792 #size-cells = <2>;
0793 #interrupt-cells = <1>;
0794 interrupt-map-mask = <0 0 0 0>;
0795 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
0796 ranges;
0797 status = "disabled";
0798 };
0799
0800 pcie@1,0 {
0801 reg = <0x0800 0 0 0 0>;
0802 #address-cells = <3>;
0803 #size-cells = <2>;
0804 #interrupt-cells = <1>;
0805 interrupt-map-mask = <0 0 0 0>;
0806 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
0807 ranges;
0808 status = "disabled";
0809 };
0810
0811 pcie@2,0 {
0812 reg = <0x1000 0 0 0 0>;
0813 #address-cells = <3>;
0814 #size-cells = <2>;
0815 #interrupt-cells = <1>;
0816 interrupt-map-mask = <0 0 0 0>;
0817 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
0818 ranges;
0819 status = "disabled";
0820 };
0821 };
0822
0823 pcie0_phy: t-phy@1a149000 {
0824 compatible = "mediatek,mt7623-tphy",
0825 "mediatek,generic-tphy-v1";
0826 reg = <0 0x1a149000 0 0x0700>;
0827 #address-cells = <2>;
0828 #size-cells = <2>;
0829 ranges;
0830 status = "disabled";
0831
0832 pcie0_port: pcie-phy@1a149900 {
0833 reg = <0 0x1a149900 0 0x0700>;
0834 clocks = <&clk26m>;
0835 clock-names = "ref";
0836 #phy-cells = <1>;
0837 status = "okay";
0838 };
0839 };
0840
0841 pcie1_phy: t-phy@1a14a000 {
0842 compatible = "mediatek,mt7623-tphy",
0843 "mediatek,generic-tphy-v1";
0844 reg = <0 0x1a14a000 0 0x0700>;
0845 #address-cells = <2>;
0846 #size-cells = <2>;
0847 ranges;
0848 status = "disabled";
0849
0850 pcie1_port: pcie-phy@1a14a900 {
0851 reg = <0 0x1a14a900 0 0x0700>;
0852 clocks = <&clk26m>;
0853 clock-names = "ref";
0854 #phy-cells = <1>;
0855 status = "okay";
0856 };
0857 };
0858
0859 usb1: usb@1a1c0000 {
0860 compatible = "mediatek,mt7623-xhci",
0861 "mediatek,mtk-xhci";
0862 reg = <0 0x1a1c0000 0 0x1000>,
0863 <0 0x1a1c4700 0 0x0100>;
0864 reg-names = "mac", "ippc";
0865 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
0866 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
0867 <&topckgen CLK_TOP_ETHIF_SEL>;
0868 clock-names = "sys_ck", "ref_ck";
0869 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
0870 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
0871 status = "disabled";
0872 };
0873
0874 u3phy1: t-phy@1a1c4000 {
0875 compatible = "mediatek,mt7623-tphy",
0876 "mediatek,generic-tphy-v1";
0877 reg = <0 0x1a1c4000 0 0x0700>;
0878 #address-cells = <2>;
0879 #size-cells = <2>;
0880 ranges;
0881 status = "disabled";
0882
0883 u2port0: usb-phy@1a1c4800 {
0884 reg = <0 0x1a1c4800 0 0x0100>;
0885 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
0886 clock-names = "ref";
0887 #phy-cells = <1>;
0888 status = "okay";
0889 };
0890
0891 u3port0: usb-phy@1a1c4900 {
0892 reg = <0 0x1a1c4900 0 0x0700>;
0893 clocks = <&clk26m>;
0894 clock-names = "ref";
0895 #phy-cells = <1>;
0896 status = "okay";
0897 };
0898 };
0899
0900 usb2: usb@1a240000 {
0901 compatible = "mediatek,mt7623-xhci",
0902 "mediatek,mtk-xhci";
0903 reg = <0 0x1a240000 0 0x1000>,
0904 <0 0x1a244700 0 0x0100>;
0905 reg-names = "mac", "ippc";
0906 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
0907 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
0908 <&topckgen CLK_TOP_ETHIF_SEL>;
0909 clock-names = "sys_ck", "ref_ck";
0910 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
0911 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
0912 status = "disabled";
0913 };
0914
0915 u3phy2: t-phy@1a244000 {
0916 compatible = "mediatek,mt7623-tphy",
0917 "mediatek,generic-tphy-v1";
0918 reg = <0 0x1a244000 0 0x0700>;
0919 #address-cells = <2>;
0920 #size-cells = <2>;
0921 ranges;
0922 status = "disabled";
0923
0924 u2port1: usb-phy@1a244800 {
0925 reg = <0 0x1a244800 0 0x0100>;
0926 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
0927 clock-names = "ref";
0928 #phy-cells = <1>;
0929 status = "okay";
0930 };
0931
0932 u3port1: usb-phy@1a244900 {
0933 reg = <0 0x1a244900 0 0x0700>;
0934 clocks = <&clk26m>;
0935 clock-names = "ref";
0936 #phy-cells = <1>;
0937 status = "okay";
0938 };
0939 };
0940
0941 ethsys: syscon@1b000000 {
0942 compatible = "mediatek,mt7623-ethsys",
0943 "mediatek,mt2701-ethsys",
0944 "syscon";
0945 reg = <0 0x1b000000 0 0x1000>;
0946 #clock-cells = <1>;
0947 #reset-cells = <1>;
0948 };
0949
0950 hsdma: dma-controller@1b007000 {
0951 compatible = "mediatek,mt7623-hsdma";
0952 reg = <0 0x1b007000 0 0x1000>;
0953 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
0954 clocks = <ðsys CLK_ETHSYS_HSDMA>;
0955 clock-names = "hsdma";
0956 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
0957 #dma-cells = <1>;
0958 };
0959
0960 eth: ethernet@1b100000 {
0961 compatible = "mediatek,mt7623-eth",
0962 "mediatek,mt2701-eth",
0963 "syscon";
0964 reg = <0 0x1b100000 0 0x20000>;
0965 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
0966 <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
0967 <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
0968 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
0969 <ðsys CLK_ETHSYS_ESW>,
0970 <ðsys CLK_ETHSYS_GP1>,
0971 <ðsys CLK_ETHSYS_GP2>,
0972 <&apmixedsys CLK_APMIXED_TRGPLL>;
0973 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
0974 resets = <ðsys MT2701_ETHSYS_FE_RST>,
0975 <ðsys MT2701_ETHSYS_GMAC_RST>,
0976 <ðsys MT2701_ETHSYS_PPE_RST>;
0977 reset-names = "fe", "gmac", "ppe";
0978 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
0979 mediatek,ethsys = <ðsys>;
0980 mediatek,pctl = <&syscfg_pctl_a>;
0981 #address-cells = <1>;
0982 #size-cells = <0>;
0983 status = "disabled";
0984 };
0985
0986 crypto: crypto@1b240000 {
0987 compatible = "mediatek,eip97-crypto";
0988 reg = <0 0x1b240000 0 0x20000>;
0989 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
0990 <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
0991 <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
0992 <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
0993 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
0994 clocks = <ðsys CLK_ETHSYS_CRYPTO>;
0995 clock-names = "cryp";
0996 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
0997 status = "disabled";
0998 };
0999
1000 bdpsys: syscon@1c000000 {
1001 compatible = "mediatek,mt7623-bdpsys",
1002 "mediatek,mt2701-bdpsys",
1003 "syscon";
1004 reg = <0 0x1c000000 0 0x1000>;
1005 #clock-cells = <1>;
1006 };
1007 };
1008
1009 &pio {
1010 cir_pins_a:cir-default {
1011 pins-cir {
1012 pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
1013 bias-disable;
1014 };
1015 };
1016
1017 i2c0_pins_a: i2c0-default {
1018 pins-i2c0 {
1019 pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
1020 <MT7623_PIN_76_SCL0_FUNC_SCL0>;
1021 bias-disable;
1022 };
1023 };
1024
1025 i2c1_pins_a: i2c1-default {
1026 pin-i2c1 {
1027 pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
1028 <MT7623_PIN_58_SCL1_FUNC_SCL1>;
1029 bias-disable;
1030 };
1031 };
1032
1033 i2c1_pins_b: i2c1-alt {
1034 pin-i2c1 {
1035 pinmux = <MT7623_PIN_242_URTS2_FUNC_SCL1>,
1036 <MT7623_PIN_243_UCTS2_FUNC_SDA1>;
1037 bias-disable;
1038 };
1039 };
1040
1041 i2c2_pins_a: i2c2-default {
1042 pin-i2c2 {
1043 pinmux = <MT7623_PIN_77_SDA2_FUNC_SDA2>,
1044 <MT7623_PIN_78_SCL2_FUNC_SCL2>;
1045 bias-disable;
1046 };
1047 };
1048
1049 i2c2_pins_b: i2c2-alt {
1050 pin-i2c2 {
1051 pinmux = <MT7623_PIN_122_GPIO122_FUNC_SDA2>,
1052 <MT7623_PIN_123_HTPLG_FUNC_SCL2>;
1053 bias-disable;
1054 };
1055 };
1056
1057 i2s0_pins_a: i2s0-default {
1058 pin-i2s0 {
1059 pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
1060 <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
1061 <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
1062 <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
1063 <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
1064 drive-strength = <MTK_DRIVE_12mA>;
1065 bias-pull-down;
1066 };
1067 };
1068
1069 i2s1_pins_a: i2s1-default {
1070 pin-i2s1 {
1071 pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
1072 <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
1073 <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
1074 <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
1075 <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
1076 drive-strength = <MTK_DRIVE_12mA>;
1077 bias-pull-down;
1078 };
1079 };
1080
1081 key_pins_a: keys-alt {
1082 pins-keys {
1083 pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
1084 <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
1085 input-enable;
1086 };
1087 };
1088
1089 led_pins_a: leds-alt {
1090 pins-leds {
1091 pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
1092 <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
1093 <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
1094 };
1095 };
1096
1097 mmc0_pins_default: mmc0default {
1098 pins-cmd-dat {
1099 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1100 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1101 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1102 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1103 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1104 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1105 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1106 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1107 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1108 input-enable;
1109 bias-pull-up;
1110 };
1111
1112 pins-clk {
1113 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1114 bias-pull-down;
1115 };
1116
1117 pins-rst {
1118 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1119 bias-pull-up;
1120 };
1121 };
1122
1123 mmc0_pins_uhs: mmc0 {
1124 pins-cmd-dat {
1125 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1126 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1127 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1128 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1129 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1130 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1131 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1132 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1133 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1134 input-enable;
1135 drive-strength = <MTK_DRIVE_2mA>;
1136 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1137 };
1138
1139 pins-clk {
1140 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1141 drive-strength = <MTK_DRIVE_2mA>;
1142 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
1143 };
1144
1145 pins-rst {
1146 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1147 bias-pull-up;
1148 };
1149 };
1150
1151 mmc1_pins_default: mmc1default {
1152 pins-cmd-dat {
1153 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1154 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1155 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1156 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1157 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1158 input-enable;
1159 drive-strength = <MTK_DRIVE_4mA>;
1160 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1161 };
1162
1163 pins-clk {
1164 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1165 bias-pull-down;
1166 drive-strength = <MTK_DRIVE_4mA>;
1167 };
1168
1169 pins-wp {
1170 pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
1171 input-enable;
1172 bias-pull-up;
1173 };
1174
1175 pins-insert {
1176 pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
1177 bias-pull-up;
1178 };
1179 };
1180
1181 mmc1_pins_uhs: mmc1 {
1182 pins-cmd-dat {
1183 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1184 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1185 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1186 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1187 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1188 input-enable;
1189 drive-strength = <MTK_DRIVE_4mA>;
1190 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1191 };
1192
1193 pins-clk {
1194 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1195 drive-strength = <MTK_DRIVE_4mA>;
1196 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1197 };
1198 };
1199
1200 nand_pins_default: nanddefault {
1201 pins-ale {
1202 pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
1203 drive-strength = <MTK_DRIVE_8mA>;
1204 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1205 };
1206
1207 pins-dat {
1208 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
1209 <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
1210 <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
1211 <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
1212 <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
1213 <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
1214 <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
1215 <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
1216 <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
1217 input-enable;
1218 drive-strength = <MTK_DRIVE_8mA>;
1219 bias-pull-up;
1220 };
1221
1222 pins-we {
1223 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
1224 drive-strength = <MTK_DRIVE_8mA>;
1225 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1226 };
1227 };
1228
1229 pcie_default: pcie_pin_default {
1230 pins_cmd_dat {
1231 pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
1232 <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
1233 bias-disable;
1234 };
1235 };
1236
1237 pwm_pins_a: pwm-default {
1238 pins-pwm {
1239 pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
1240 <MT7623_PIN_204_PWM1_FUNC_PWM1>,
1241 <MT7623_PIN_205_PWM2_FUNC_PWM2>,
1242 <MT7623_PIN_206_PWM3_FUNC_PWM3>,
1243 <MT7623_PIN_207_PWM4_FUNC_PWM4>;
1244 };
1245 };
1246
1247 spi0_pins_a: spi0-default {
1248 pins-spi {
1249 pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
1250 <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
1251 <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
1252 <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
1253 bias-disable;
1254 };
1255 };
1256
1257 spi1_pins_a: spi1-default {
1258 pins-spi {
1259 pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>,
1260 <MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>,
1261 <MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>,
1262 <MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>;
1263 };
1264 };
1265
1266 spi2_pins_a: spi2-default {
1267 pins-spi {
1268 pinmux = <MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS>,
1269 <MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK>,
1270 <MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI>,
1271 <MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO>;
1272 };
1273 };
1274
1275 uart0_pins_a: uart0-default {
1276 pins-dat {
1277 pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
1278 <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
1279 };
1280 };
1281
1282 uart1_pins_a: uart1-default {
1283 pins-dat {
1284 pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
1285 <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
1286 };
1287 };
1288
1289 uart2_pins_a: uart2-default {
1290 pins-dat {
1291 pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
1292 <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
1293 };
1294 };
1295
1296 uart2_pins_b: uart2-alt {
1297 pins-dat {
1298 pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
1299 <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;
1300 };
1301 };
1302 };
