0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (c) 2014 MediaTek Inc.
0004 * Author: Howard Chen <ibanezchen@gmail.com>
0005 *
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010
0011 / {
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 compatible = "mediatek,mt6592";
0015 interrupt-parent = <&sysirq>;
0016
0017 cpus {
0018 #address-cells = <1>;
0019 #size-cells = <0>;
0020
0021 cpu@0 {
0022 device_type = "cpu";
0023 compatible = "arm,cortex-a7";
0024 reg = <0x0>;
0025 };
0026 cpu@1 {
0027 device_type = "cpu";
0028 compatible = "arm,cortex-a7";
0029 reg = <0x1>;
0030 };
0031 cpu@2 {
0032 device_type = "cpu";
0033 compatible = "arm,cortex-a7";
0034 reg = <0x2>;
0035 };
0036 cpu@3 {
0037 device_type = "cpu";
0038 compatible = "arm,cortex-a7";
0039 reg = <0x3>;
0040 };
0041 cpu@4 {
0042 device_type = "cpu";
0043 compatible = "arm,cortex-a7";
0044 reg = <0x4>;
0045 };
0046 cpu@5 {
0047 device_type = "cpu";
0048 compatible = "arm,cortex-a7";
0049 reg = <0x5>;
0050 };
0051 cpu@6 {
0052 device_type = "cpu";
0053 compatible = "arm,cortex-a7";
0054 reg = <0x6>;
0055 };
0056 cpu@7 {
0057 device_type = "cpu";
0058 compatible = "arm,cortex-a7";
0059 reg = <0x7>;
0060 };
0061 };
0062
0063 system_clk: dummy13m {
0064 compatible = "fixed-clock";
0065 clock-frequency = <13000000>;
0066 #clock-cells = <0>;
0067 };
0068
0069 rtc_clk: dummy32k {
0070 compatible = "fixed-clock";
0071 clock-frequency = <32000>;
0072 #clock-cells = <0>;
0073 };
0074
0075 uart_clk: dummy26m {
0076 compatible = "fixed-clock";
0077 clock-frequency = <26000000>;
0078 #clock-cells = <0>;
0079 };
0080
0081 timer: timer@10008000 {
0082 compatible = "mediatek,mt6577-timer";
0083 reg = <0x10008000 0x80>;
0084 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
0085 clocks = <&system_clk>, <&rtc_clk>;
0086 clock-names = "system-clk", "rtc-clk";
0087 };
0088
0089 sysirq: interrupt-controller@10200220 {
0090 compatible = "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq";
0091 interrupt-controller;
0092 #interrupt-cells = <3>;
0093 interrupt-parent = <&gic>;
0094 reg = <0x10200220 0x1c>;
0095 };
0096
0097 gic: interrupt-controller@10211000 {
0098 compatible = "arm,cortex-a7-gic";
0099 interrupt-controller;
0100 #interrupt-cells = <3>;
0101 interrupt-parent = <&gic>;
0102 reg = <0x10211000 0x1000>,
0103 <0x10212000 0x1000>;
0104 };
0105
0106 uart0: serial@11002000 {
0107 compatible = "mediatek,mt6577-uart";
0108 reg = <0x11002000 0x400>;
0109 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
0110 clocks = <&uart_clk>;
0111 status = "disabled";
0112 };
0113
0114 uart1: serial@11003000 {
0115 compatible = "mediatek,mt6577-uart";
0116 reg = <0x11003000 0x400>;
0117 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
0118 clocks = <&uart_clk>;
0119 status = "disabled";
0120 };
0121
0122 uart2: serial@11004000 {
0123 compatible = "mediatek,mt6577-uart";
0124 reg = <0x11004000 0x400>;
0125 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
0126 clocks = <&uart_clk>;
0127 status = "disabled";
0128 };
0129
0130 uart3: serial@11005000 {
0131 compatible = "mediatek,mt6577-uart";
0132 reg = <0x11005000 0x400>;
0133 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
0134 clocks = <&uart_clk>;
0135 status = "disabled";
0136 };
0137 };
