0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright (c) 2014 MundoReader S.L.
0004 * Author: Matthias Brugger <matthias.bgg@gmail.com>
0005 *
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010
0011 / {
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 compatible = "mediatek,mt6589";
0015 interrupt-parent = <&sysirq>;
0016
0017 cpus: cpus {
0018 #address-cells = <1>;
0019 #size-cells = <0>;
0020 enable-method = "mediatek,mt6589-smp";
0021
0022 cpu@0 {
0023 device_type = "cpu";
0024 compatible = "arm,cortex-a7";
0025 reg = <0x0>;
0026 };
0027 cpu@1 {
0028 device_type = "cpu";
0029 compatible = "arm,cortex-a7";
0030 reg = <0x1>;
0031 };
0032 cpu@2 {
0033 device_type = "cpu";
0034 compatible = "arm,cortex-a7";
0035 reg = <0x2>;
0036 };
0037 cpu@3 {
0038 device_type = "cpu";
0039 compatible = "arm,cortex-a7";
0040 reg = <0x3>;
0041 };
0042
0043 };
0044
0045 clocks {
0046 #address-cells = <1>;
0047 #size-cells = <1>;
0048 compatible = "simple-bus";
0049 ranges;
0050
0051 system_clk: dummy13m {
0052 compatible = "fixed-clock";
0053 clock-frequency = <13000000>;
0054 #clock-cells = <0>;
0055 };
0056
0057 rtc_clk: dummy32k {
0058 compatible = "fixed-clock";
0059 clock-frequency = <32000>;
0060 #clock-cells = <0>;
0061 };
0062
0063 uart_clk: dummy26m {
0064 compatible = "fixed-clock";
0065 clock-frequency = <26000000>;
0066 #clock-cells = <0>;
0067 };
0068 };
0069
0070 soc {
0071 #address-cells = <1>;
0072 #size-cells = <1>;
0073 compatible = "simple-bus";
0074 ranges;
0075
0076 timer: timer@10008000 {
0077 compatible = "mediatek,mt6577-timer";
0078 reg = <0x10008000 0x80>;
0079 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
0080 clocks = <&system_clk>, <&rtc_clk>;
0081 clock-names = "system-clk", "rtc-clk";
0082 };
0083
0084 sysirq: interrupt-controller@10200100 {
0085 compatible = "mediatek,mt6589-sysirq",
0086 "mediatek,mt6577-sysirq";
0087 interrupt-controller;
0088 #interrupt-cells = <3>;
0089 interrupt-parent = <&gic>;
0090 reg = <0x10200100 0x1c>;
0091 };
0092
0093 gic: interrupt-controller@10211000 {
0094 compatible = "arm,cortex-a7-gic";
0095 interrupt-controller;
0096 #interrupt-cells = <3>;
0097 interrupt-parent = <&gic>;
0098 reg = <0x10211000 0x1000>,
0099 <0x10212000 0x2000>,
0100 <0x10214000 0x2000>,
0101 <0x10216000 0x2000>;
0102 };
0103
0104 uart0: serial@11006000 {
0105 compatible = "mediatek,mt6577-uart";
0106 reg = <0x11006000 0x400>;
0107 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
0108 clocks = <&uart_clk>;
0109 status = "disabled";
0110 };
0111
0112 uart1: serial@11007000 {
0113 compatible = "mediatek,mt6577-uart";
0114 reg = <0x11007000 0x400>;
0115 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
0116 clocks = <&uart_clk>;
0117 status = "disabled";
0118 };
0119
0120 uart2: serial@11008000 {
0121 compatible = "mediatek,mt6577-uart";
0122 reg = <0x11008000 0x400>;
0123 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
0124 clocks = <&uart_clk>;
0125 status = "disabled";
0126 };
0127
0128 uart3: serial@11009000 {
0129 compatible = "mediatek,mt6577-uart";
0130 reg = <0x11009000 0x400>;
0131 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
0132 clocks = <&uart_clk>;
0133 status = "disabled";
0134 };
0135
0136 wdt: watchdog@10000000 {
0137 compatible = "mediatek,mt6589-wdt";
0138 reg = <0x10000000 0x44>;
0139 };
0140 };
0141 };
