0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright (c) 2021 Maxim Kutnij <gtk3@inbox.ru>
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/irq.h>
0007 #include <dt-bindings/interrupt-controller/arm-gic.h>
0008
0009 / {
0010 #address-cells = <1>;
0011 #size-cells = <1>;
0012 compatible = "mediatek,mt6582";
0013 interrupt-parent = <&sysirq>;
0014
0015 cpus {
0016 #address-cells = <1>;
0017 #size-cells = <0>;
0018
0019 cpu@0 {
0020 device_type = "cpu";
0021 compatible = "arm,cortex-a7";
0022 reg = <0x0>;
0023 };
0024 cpu@1 {
0025 device_type = "cpu";
0026 compatible = "arm,cortex-a7";
0027 reg = <0x1>;
0028 };
0029 cpu@2 {
0030 device_type = "cpu";
0031 compatible = "arm,cortex-a7";
0032 reg = <0x2>;
0033 };
0034 cpu@3 {
0035 device_type = "cpu";
0036 compatible = "arm,cortex-a7";
0037 reg = <0x3>;
0038 };
0039 };
0040
0041 system_clk: dummy13m {
0042 compatible = "fixed-clock";
0043 clock-frequency = <13000000>;
0044 #clock-cells = <0>;
0045 };
0046
0047 rtc_clk: dummy32k {
0048 compatible = "fixed-clock";
0049 clock-frequency = <32000>;
0050 #clock-cells = <0>;
0051 };
0052
0053 uart_clk: dummy26m {
0054 compatible = "fixed-clock";
0055 clock-frequency = <26000000>;
0056 #clock-cells = <0>;
0057 };
0058
0059 timer: timer@11008000 {
0060 compatible = "mediatek,mt6577-timer";
0061 reg = <0x10008000 0x80>;
0062 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
0063 clocks = <&system_clk>, <&rtc_clk>;
0064 clock-names = "system-clk", "rtc-clk";
0065 };
0066
0067 sysirq: interrupt-controller@10200100 {
0068 compatible = "mediatek,mt6582-sysirq",
0069 "mediatek,mt6577-sysirq";
0070 interrupt-controller;
0071 #interrupt-cells = <3>;
0072 interrupt-parent = <&gic>;
0073 reg = <0x10200100 0x1c>;
0074 };
0075
0076 gic: interrupt-controller@10211000 {
0077 compatible = "arm,cortex-a7-gic";
0078 interrupt-controller;
0079 #interrupt-cells = <3>;
0080 interrupt-parent = <&gic>;
0081 reg = <0x10211000 0x1000>,
0082 <0x10212000 0x2000>,
0083 <0x10214000 0x2000>,
0084 <0x10216000 0x2000>;
0085 };
0086
0087 uart0: serial@11002000 {
0088 compatible = "mediatek,mt6582-uart",
0089 "mediatek,mt6577-uart";
0090 reg = <0x11002000 0x400>;
0091 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
0092 clocks = <&uart_clk>;
0093 status = "disabled";
0094 };
0095
0096 uart1: serial@11003000 {
0097 compatible = "mediatek,mt6582-uart",
0098 "mediatek,mt6577-uart";
0099 reg = <0x11003000 0x400>;
0100 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
0101 clocks = <&uart_clk>;
0102 status = "disabled";
0103 };
0104
0105 uart2: serial@11004000 {
0106 compatible = "mediatek,mt6582-uart",
0107 "mediatek,mt6577-uart";
0108 reg = <0x11004000 0x400>;
0109 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
0110 clocks = <&uart_clk>;
0111 status = "disabled";
0112 };
0113
0114 uart3: serial@11005000 {
0115 compatible = "mediatek,mt6582-uart",
0116 "mediatek,mt6577-uart";
0117 reg = <0x11005000 0x400>;
0118 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
0119 clocks = <&uart_clk>;
0120 status = "disabled";
0121 };
0122
0123 watchdog: watchdog@10007000 {
0124 compatible = "mediatek,mt6582-wdt",
0125 "mediatek,mt6589-wdt";
0126 reg = <0x10007000 0x100>;
0127 };
0128 };
