0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (c) 2015 MediaTek Inc.
0004 * Author: Mars.C <mars.cheng@mediatek.com>
0005 *
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010
0011 / {
0012 compatible = "mediatek,mt6580";
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015 interrupt-parent = <&sysirq>;
0016
0017 cpus {
0018 #address-cells = <1>;
0019 #size-cells = <0>;
0020
0021 cpu@0 {
0022 device_type = "cpu";
0023 compatible = "arm,cortex-a7";
0024 reg = <0x0>;
0025 };
0026 cpu@1 {
0027 device_type = "cpu";
0028 compatible = "arm,cortex-a7";
0029 reg = <0x1>;
0030 };
0031 cpu@2 {
0032 device_type = "cpu";
0033 compatible = "arm,cortex-a7";
0034 reg = <0x2>;
0035 };
0036 cpu@3 {
0037 device_type = "cpu";
0038 compatible = "arm,cortex-a7";
0039 reg = <0x3>;
0040 };
0041
0042 };
0043
0044 system_clk: dummy13m {
0045 compatible = "fixed-clock";
0046 clock-frequency = <13000000>;
0047 #clock-cells = <0>;
0048 };
0049
0050 rtc_clk: dummy32k {
0051 compatible = "fixed-clock";
0052 clock-frequency = <32000>;
0053 #clock-cells = <0>;
0054 };
0055
0056 uart_clk: dummy26m {
0057 compatible = "fixed-clock";
0058 clock-frequency = <26000000>;
0059 #clock-cells = <0>;
0060 };
0061
0062 timer: timer@10008000 {
0063 compatible = "mediatek,mt6580-timer",
0064 "mediatek,mt6577-timer";
0065 reg = <0x10008000 0x80>;
0066 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
0067 clocks = <&system_clk>, <&rtc_clk>;
0068 clock-names = "system-clk", "rtc-clk";
0069 };
0070
0071 sysirq: interrupt-controller@10200100 {
0072 compatible = "mediatek,mt6580-sysirq",
0073 "mediatek,mt6577-sysirq";
0074 interrupt-controller;
0075 #interrupt-cells = <3>;
0076 interrupt-parent = <&gic>;
0077 reg = <0x10200100 0x1c>;
0078 };
0079
0080 gic: interrupt-controller@10211000 {
0081 compatible = "arm,cortex-a7-gic";
0082 interrupt-controller;
0083 #interrupt-cells = <3>;
0084 interrupt-parent = <&gic>;
0085 reg = <0x10211000 0x1000>,
0086 <0x10212000 0x2000>,
0087 <0x10214000 0x2000>,
0088 <0x10216000 0x2000>;
0089 };
0090
0091 uart0: serial@11005000 {
0092 compatible = "mediatek,mt6580-uart",
0093 "mediatek,mt6577-uart";
0094 reg = <0x11005000 0x400>;
0095 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
0096 clocks = <&uart_clk>;
0097 status = "disabled";
0098 };
0099
0100 uart1: serial@11006000 {
0101 compatible = "mediatek,mt6580-uart",
0102 "mediatek,mt6577-uart";
0103 reg = <0x11006000 0x400>;
0104 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
0105 clocks = <&uart_clk>;
0106 status = "disabled";
0107 };
0108 };
