0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (c) 2015 MediaTek Inc.
0004 * Author: Erin.Lo <erin.lo@mediatek.com>
0005 *
0006 */
0007
0008 #include <dt-bindings/clock/mt2701-clk.h>
0009 #include <dt-bindings/phy/phy.h>
0010 #include <dt-bindings/power/mt2701-power.h>
0011 #include <dt-bindings/interrupt-controller/irq.h>
0012 #include <dt-bindings/interrupt-controller/arm-gic.h>
0013 #include <dt-bindings/memory/mt2701-larb-port.h>
0014 #include <dt-bindings/reset/mt2701-resets.h>
0015 #include "mt2701-pinfunc.h"
0016
0017 / {
0018 #address-cells = <2>;
0019 #size-cells = <2>;
0020 compatible = "mediatek,mt2701";
0021 interrupt-parent = <&cirq>;
0022
0023 cpus {
0024 #address-cells = <1>;
0025 #size-cells = <0>;
0026 enable-method = "mediatek,mt81xx-tz-smp";
0027
0028 cpu@0 {
0029 device_type = "cpu";
0030 compatible = "arm,cortex-a7";
0031 reg = <0x0>;
0032 };
0033 cpu@1 {
0034 device_type = "cpu";
0035 compatible = "arm,cortex-a7";
0036 reg = <0x1>;
0037 };
0038 cpu@2 {
0039 device_type = "cpu";
0040 compatible = "arm,cortex-a7";
0041 reg = <0x2>;
0042 };
0043 cpu@3 {
0044 device_type = "cpu";
0045 compatible = "arm,cortex-a7";
0046 reg = <0x3>;
0047 };
0048 };
0049
0050 reserved-memory {
0051 #address-cells = <2>;
0052 #size-cells = <2>;
0053 ranges;
0054
0055 trustzone-bootinfo@80002000 {
0056 compatible = "mediatek,trustzone-bootinfo";
0057 reg = <0 0x80002000 0 0x1000>;
0058 };
0059 };
0060
0061 system_clk: dummy13m {
0062 compatible = "fixed-clock";
0063 clock-frequency = <13000000>;
0064 #clock-cells = <0>;
0065 };
0066
0067 rtc_clk: dummy32k {
0068 compatible = "fixed-clock";
0069 clock-frequency = <32000>;
0070 #clock-cells = <0>;
0071 };
0072
0073 clk26m: oscillator@0 {
0074 compatible = "fixed-clock";
0075 #clock-cells = <0>;
0076 clock-frequency = <26000000>;
0077 clock-output-names = "clk26m";
0078 };
0079
0080 rtc32k: oscillator@1 {
0081 compatible = "fixed-clock";
0082 #clock-cells = <0>;
0083 clock-frequency = <32000>;
0084 clock-output-names = "rtc32k";
0085 };
0086
0087 thermal-zones {
0088 cpu_thermal: cpu_thermal {
0089 polling-delay-passive = <1000>; /* milliseconds */
0090 polling-delay = <1000>; /* milliseconds */
0091
0092 thermal-sensors = <&thermal 0>;
0093 sustainable-power = <1000>;
0094
0095 trips {
0096 threshold: trip-point@0 {
0097 temperature = <68000>;
0098 hysteresis = <2000>;
0099 type = "passive";
0100 };
0101
0102 target: trip-point@1 {
0103 temperature = <85000>;
0104 hysteresis = <2000>;
0105 type = "passive";
0106 };
0107
0108 cpu_crit: cpu_crit@0 {
0109 temperature = <115000>;
0110 hysteresis = <2000>;
0111 type = "critical";
0112 };
0113 };
0114 };
0115 };
0116
0117 timer {
0118 compatible = "arm,armv7-timer";
0119 interrupt-parent = <&gic>;
0120 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0121 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0122 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0123 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0124 };
0125
0126 topckgen: syscon@10000000 {
0127 compatible = "mediatek,mt2701-topckgen", "syscon";
0128 reg = <0 0x10000000 0 0x1000>;
0129 #clock-cells = <1>;
0130 };
0131
0132 infracfg: syscon@10001000 {
0133 compatible = "mediatek,mt2701-infracfg", "syscon";
0134 reg = <0 0x10001000 0 0x1000>;
0135 #clock-cells = <1>;
0136 #reset-cells = <1>;
0137 };
0138
0139 pericfg: syscon@10003000 {
0140 compatible = "mediatek,mt2701-pericfg", "syscon";
0141 reg = <0 0x10003000 0 0x1000>;
0142 #clock-cells = <1>;
0143 #reset-cells = <1>;
0144 };
0145
0146 syscfg_pctl_a: syscfg@10005000 {
0147 compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
0148 reg = <0 0x10005000 0 0x1000>;
0149 };
0150
0151 scpsys: power-controller@10006000 {
0152 compatible = "mediatek,mt2701-scpsys", "syscon";
0153 #power-domain-cells = <1>;
0154 reg = <0 0x10006000 0 0x1000>;
0155 infracfg = <&infracfg>;
0156 clocks = <&topckgen CLK_TOP_MM_SEL>,
0157 <&topckgen CLK_TOP_MFG_SEL>,
0158 <&topckgen CLK_TOP_ETHIF_SEL>;
0159 clock-names = "mm", "mfg", "ethif";
0160 };
0161
0162 watchdog: watchdog@10007000 {
0163 compatible = "mediatek,mt2701-wdt",
0164 "mediatek,mt6589-wdt";
0165 reg = <0 0x10007000 0 0x100>;
0166 };
0167
0168 timer: timer@10008000 {
0169 compatible = "mediatek,mt2701-timer",
0170 "mediatek,mt6577-timer";
0171 reg = <0 0x10008000 0 0x80>;
0172 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
0173 clocks = <&system_clk>, <&rtc_clk>;
0174 clock-names = "system-clk", "rtc-clk";
0175 };
0176
0177 pio: pinctrl@1000b000 {
0178 compatible = "mediatek,mt2701-pinctrl";
0179 reg = <0 0x1000b000 0 0x1000>;
0180 mediatek,pctl-regmap = <&syscfg_pctl_a>;
0181 pins-are-numbered;
0182 gpio-controller;
0183 #gpio-cells = <2>;
0184 interrupt-controller;
0185 #interrupt-cells = <2>;
0186 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
0187 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0188 };
0189
0190 smi_common: smi@1000c000 {
0191 compatible = "mediatek,mt2701-smi-common";
0192 reg = <0 0x1000c000 0 0x1000>;
0193 clocks = <&infracfg CLK_INFRA_SMI>,
0194 <&mmsys CLK_MM_SMI_COMMON>,
0195 <&infracfg CLK_INFRA_SMI>;
0196 clock-names = "apb", "smi", "async";
0197 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
0198 };
0199
0200 sysirq: interrupt-controller@10200100 {
0201 compatible = "mediatek,mt2701-sysirq",
0202 "mediatek,mt6577-sysirq";
0203 interrupt-controller;
0204 #interrupt-cells = <3>;
0205 interrupt-parent = <&gic>;
0206 reg = <0 0x10200100 0 0x1c>;
0207 };
0208
0209 cirq: interrupt-controller@10204000 {
0210 compatible = "mediatek,mt2701-cirq",
0211 "mediatek,mtk-cirq";
0212 interrupt-controller;
0213 #interrupt-cells = <3>;
0214 interrupt-parent = <&sysirq>;
0215 reg = <0 0x10204000 0 0x400>;
0216 mediatek,ext-irq-range = <32 200>;
0217 };
0218
0219 iommu: mmsys_iommu@10205000 {
0220 compatible = "mediatek,mt2701-m4u";
0221 reg = <0 0x10205000 0 0x1000>;
0222 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
0223 clocks = <&infracfg CLK_INFRA_M4U>;
0224 clock-names = "bclk";
0225 mediatek,larbs = <&larb0 &larb1 &larb2>;
0226 #iommu-cells = <1>;
0227 };
0228
0229 apmixedsys: syscon@10209000 {
0230 compatible = "mediatek,mt2701-apmixedsys", "syscon";
0231 reg = <0 0x10209000 0 0x1000>;
0232 #clock-cells = <1>;
0233 };
0234
0235 gic: interrupt-controller@10211000 {
0236 compatible = "arm,cortex-a7-gic";
0237 interrupt-controller;
0238 #interrupt-cells = <3>;
0239 interrupt-parent = <&gic>;
0240 reg = <0 0x10211000 0 0x1000>,
0241 <0 0x10212000 0 0x2000>,
0242 <0 0x10214000 0 0x2000>,
0243 <0 0x10216000 0 0x2000>;
0244 };
0245
0246 auxadc: adc@11001000 {
0247 compatible = "mediatek,mt2701-auxadc";
0248 reg = <0 0x11001000 0 0x1000>;
0249 clocks = <&pericfg CLK_PERI_AUXADC>;
0250 clock-names = "main";
0251 #io-channel-cells = <1>;
0252 status = "disabled";
0253 };
0254
0255 uart0: serial@11002000 {
0256 compatible = "mediatek,mt2701-uart",
0257 "mediatek,mt6577-uart";
0258 reg = <0 0x11002000 0 0x400>;
0259 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
0260 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
0261 clock-names = "baud", "bus";
0262 status = "disabled";
0263 };
0264
0265 uart1: serial@11003000 {
0266 compatible = "mediatek,mt2701-uart",
0267 "mediatek,mt6577-uart";
0268 reg = <0 0x11003000 0 0x400>;
0269 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
0270 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
0271 clock-names = "baud", "bus";
0272 status = "disabled";
0273 };
0274
0275 uart2: serial@11004000 {
0276 compatible = "mediatek,mt2701-uart",
0277 "mediatek,mt6577-uart";
0278 reg = <0 0x11004000 0 0x400>;
0279 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
0280 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
0281 clock-names = "baud", "bus";
0282 status = "disabled";
0283 };
0284
0285 uart3: serial@11005000 {
0286 compatible = "mediatek,mt2701-uart",
0287 "mediatek,mt6577-uart";
0288 reg = <0 0x11005000 0 0x400>;
0289 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
0290 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
0291 clock-names = "baud", "bus";
0292 status = "disabled";
0293 };
0294
0295 i2c0: i2c@11007000 {
0296 compatible = "mediatek,mt2701-i2c",
0297 "mediatek,mt6577-i2c";
0298 reg = <0 0x11007000 0 0x70>,
0299 <0 0x11000200 0 0x80>;
0300 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
0301 clock-div = <16>;
0302 clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
0303 clock-names = "main", "dma";
0304 #address-cells = <1>;
0305 #size-cells = <0>;
0306 status = "disabled";
0307 };
0308
0309 i2c1: i2c@11008000 {
0310 compatible = "mediatek,mt2701-i2c",
0311 "mediatek,mt6577-i2c";
0312 reg = <0 0x11008000 0 0x70>,
0313 <0 0x11000280 0 0x80>;
0314 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
0315 clock-div = <16>;
0316 clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
0317 clock-names = "main", "dma";
0318 #address-cells = <1>;
0319 #size-cells = <0>;
0320 status = "disabled";
0321 };
0322
0323 i2c2: i2c@11009000 {
0324 compatible = "mediatek,mt2701-i2c",
0325 "mediatek,mt6577-i2c";
0326 reg = <0 0x11009000 0 0x70>,
0327 <0 0x11000300 0 0x80>;
0328 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
0329 clock-div = <16>;
0330 clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
0331 clock-names = "main", "dma";
0332 #address-cells = <1>;
0333 #size-cells = <0>;
0334 status = "disabled";
0335 };
0336
0337 spi0: spi@1100a000 {
0338 compatible = "mediatek,mt2701-spi";
0339 #address-cells = <1>;
0340 #size-cells = <0>;
0341 reg = <0 0x1100a000 0 0x100>;
0342 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
0343 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
0344 <&topckgen CLK_TOP_SPI0_SEL>,
0345 <&pericfg CLK_PERI_SPI0>;
0346 clock-names = "parent-clk", "sel-clk", "spi-clk";
0347 status = "disabled";
0348 };
0349
0350 thermal: thermal@1100b000 {
0351 #thermal-sensor-cells = <0>;
0352 compatible = "mediatek,mt2701-thermal";
0353 reg = <0 0x1100b000 0 0x1000>;
0354 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
0355 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
0356 clock-names = "therm", "auxadc";
0357 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
0358 reset-names = "therm";
0359 mediatek,auxadc = <&auxadc>;
0360 mediatek,apmixedsys = <&apmixedsys>;
0361 };
0362
0363 nandc: nfi@1100d000 {
0364 compatible = "mediatek,mt2701-nfc";
0365 reg = <0 0x1100d000 0 0x1000>;
0366 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
0367 clocks = <&pericfg CLK_PERI_NFI>,
0368 <&pericfg CLK_PERI_NFI_PAD>;
0369 clock-names = "nfi_clk", "pad_clk";
0370 status = "disabled";
0371 ecc-engine = <&bch>;
0372 #address-cells = <1>;
0373 #size-cells = <0>;
0374 };
0375
0376 bch: ecc@1100e000 {
0377 compatible = "mediatek,mt2701-ecc";
0378 reg = <0 0x1100e000 0 0x1000>;
0379 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
0380 clocks = <&pericfg CLK_PERI_NFI_ECC>;
0381 clock-names = "nfiecc_clk";
0382 status = "disabled";
0383 };
0384
0385 nor_flash: spi@11014000 {
0386 compatible = "mediatek,mt2701-nor",
0387 "mediatek,mt8173-nor";
0388 reg = <0 0x11014000 0 0xe0>;
0389 clocks = <&pericfg CLK_PERI_FLASH>,
0390 <&topckgen CLK_TOP_FLASH_SEL>;
0391 clock-names = "spi", "sf";
0392 #address-cells = <1>;
0393 #size-cells = <0>;
0394 status = "disabled";
0395 };
0396
0397 spi1: spi@11016000 {
0398 compatible = "mediatek,mt2701-spi";
0399 #address-cells = <1>;
0400 #size-cells = <0>;
0401 reg = <0 0x11016000 0 0x100>;
0402 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
0403 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
0404 <&topckgen CLK_TOP_SPI1_SEL>,
0405 <&pericfg CLK_PERI_SPI1>;
0406 clock-names = "parent-clk", "sel-clk", "spi-clk";
0407 status = "disabled";
0408 };
0409
0410 spi2: spi@11017000 {
0411 compatible = "mediatek,mt2701-spi";
0412 #address-cells = <1>;
0413 #size-cells = <0>;
0414 reg = <0 0x11017000 0 0x1000>;
0415 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
0416 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
0417 <&topckgen CLK_TOP_SPI2_SEL>,
0418 <&pericfg CLK_PERI_SPI2>;
0419 clock-names = "parent-clk", "sel-clk", "spi-clk";
0420 status = "disabled";
0421 };
0422
0423 audsys: clock-controller@11220000 {
0424 compatible = "mediatek,mt2701-audsys", "syscon";
0425 reg = <0 0x11220000 0 0x2000>;
0426 #clock-cells = <1>;
0427
0428 afe: audio-controller {
0429 compatible = "mediatek,mt2701-audio";
0430 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
0431 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
0432 interrupt-names = "afe", "asys";
0433 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
0434
0435 clocks = <&infracfg CLK_INFRA_AUDIO>,
0436 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
0437 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
0438 <&topckgen CLK_TOP_AUD_48K_TIMING>,
0439 <&topckgen CLK_TOP_AUD_44K_TIMING>,
0440 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
0441 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
0442 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
0443 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
0444 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
0445 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
0446 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
0447 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
0448 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
0449 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
0450 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
0451 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
0452 <&audsys CLK_AUD_I2SO1>,
0453 <&audsys CLK_AUD_I2SO2>,
0454 <&audsys CLK_AUD_I2SO3>,
0455 <&audsys CLK_AUD_I2SO4>,
0456 <&audsys CLK_AUD_I2SIN1>,
0457 <&audsys CLK_AUD_I2SIN2>,
0458 <&audsys CLK_AUD_I2SIN3>,
0459 <&audsys CLK_AUD_I2SIN4>,
0460 <&audsys CLK_AUD_ASRCO1>,
0461 <&audsys CLK_AUD_ASRCO2>,
0462 <&audsys CLK_AUD_ASRCO3>,
0463 <&audsys CLK_AUD_ASRCO4>,
0464 <&audsys CLK_AUD_AFE>,
0465 <&audsys CLK_AUD_AFE_CONN>,
0466 <&audsys CLK_AUD_A1SYS>,
0467 <&audsys CLK_AUD_A2SYS>,
0468 <&audsys CLK_AUD_AFE_MRGIF>;
0469
0470 clock-names = "infra_sys_audio_clk",
0471 "top_audio_mux1_sel",
0472 "top_audio_mux2_sel",
0473 "top_audio_a1sys_hp",
0474 "top_audio_a2sys_hp",
0475 "i2s0_src_sel",
0476 "i2s1_src_sel",
0477 "i2s2_src_sel",
0478 "i2s3_src_sel",
0479 "i2s0_src_div",
0480 "i2s1_src_div",
0481 "i2s2_src_div",
0482 "i2s3_src_div",
0483 "i2s0_mclk_en",
0484 "i2s1_mclk_en",
0485 "i2s2_mclk_en",
0486 "i2s3_mclk_en",
0487 "i2so0_hop_ck",
0488 "i2so1_hop_ck",
0489 "i2so2_hop_ck",
0490 "i2so3_hop_ck",
0491 "i2si0_hop_ck",
0492 "i2si1_hop_ck",
0493 "i2si2_hop_ck",
0494 "i2si3_hop_ck",
0495 "asrc0_out_ck",
0496 "asrc1_out_ck",
0497 "asrc2_out_ck",
0498 "asrc3_out_ck",
0499 "audio_afe_pd",
0500 "audio_afe_conn_pd",
0501 "audio_a1sys_pd",
0502 "audio_a2sys_pd",
0503 "audio_mrgif_pd";
0504
0505 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
0506 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
0507 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
0508 <&topckgen CLK_TOP_AUD_MUX2_DIV>;
0509 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
0510 <&topckgen CLK_TOP_AUD2PLL_90M>;
0511 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
0512 };
0513 };
0514
0515 mmsys: syscon@14000000 {
0516 compatible = "mediatek,mt2701-mmsys", "syscon";
0517 reg = <0 0x14000000 0 0x1000>;
0518 #clock-cells = <1>;
0519 };
0520
0521 bls: pwm@1400a000 {
0522 compatible = "mediatek,mt2701-disp-pwm";
0523 reg = <0 0x1400a000 0 0x1000>;
0524 #pwm-cells = <2>;
0525 clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>;
0526 clock-names = "main", "mm";
0527 status = "disabled";
0528 };
0529
0530 larb0: larb@14010000 {
0531 compatible = "mediatek,mt2701-smi-larb";
0532 reg = <0 0x14010000 0 0x1000>;
0533 mediatek,smi = <&smi_common>;
0534 mediatek,larb-id = <0>;
0535 clocks = <&mmsys CLK_MM_SMI_LARB0>,
0536 <&mmsys CLK_MM_SMI_LARB0>;
0537 clock-names = "apb", "smi";
0538 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
0539 };
0540
0541 imgsys: syscon@15000000 {
0542 compatible = "mediatek,mt2701-imgsys", "syscon";
0543 reg = <0 0x15000000 0 0x1000>;
0544 #clock-cells = <1>;
0545 };
0546
0547 larb2: larb@15001000 {
0548 compatible = "mediatek,mt2701-smi-larb";
0549 reg = <0 0x15001000 0 0x1000>;
0550 mediatek,smi = <&smi_common>;
0551 mediatek,larb-id = <2>;
0552 clocks = <&imgsys CLK_IMG_SMI_COMM>,
0553 <&imgsys CLK_IMG_SMI_COMM>;
0554 clock-names = "apb", "smi";
0555 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
0556 };
0557
0558 jpegdec: jpegdec@15004000 {
0559 compatible = "mediatek,mt2701-jpgdec";
0560 reg = <0 0x15004000 0 0x1000>;
0561 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
0562 clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
0563 <&imgsys CLK_IMG_JPGDEC>;
0564 clock-names = "jpgdec-smi",
0565 "jpgdec";
0566 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
0567 iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
0568 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
0569 };
0570
0571 jpegenc: jpegenc@1500a000 {
0572 compatible = "mediatek,mt2701-jpgenc",
0573 "mediatek,mtk-jpgenc";
0574 reg = <0 0x1500a000 0 0x1000>;
0575 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
0576 clocks = <&imgsys CLK_IMG_VENC>;
0577 clock-names = "jpgenc";
0578 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
0579 iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
0580 <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
0581 };
0582
0583 vdecsys: syscon@16000000 {
0584 compatible = "mediatek,mt2701-vdecsys", "syscon";
0585 reg = <0 0x16000000 0 0x1000>;
0586 #clock-cells = <1>;
0587 };
0588
0589 larb1: larb@16010000 {
0590 compatible = "mediatek,mt2701-smi-larb";
0591 reg = <0 0x16010000 0 0x1000>;
0592 mediatek,smi = <&smi_common>;
0593 mediatek,larb-id = <1>;
0594 clocks = <&vdecsys CLK_VDEC_CKGEN>,
0595 <&vdecsys CLK_VDEC_LARB>;
0596 clock-names = "apb", "smi";
0597 power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
0598 };
0599
0600 hifsys: syscon@1a000000 {
0601 compatible = "mediatek,mt2701-hifsys", "syscon";
0602 reg = <0 0x1a000000 0 0x1000>;
0603 #clock-cells = <1>;
0604 #reset-cells = <1>;
0605 };
0606
0607 usb0: usb@1a1c0000 {
0608 compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci";
0609 reg = <0 0x1a1c0000 0 0x1000>,
0610 <0 0x1a1c4700 0 0x0100>;
0611 reg-names = "mac", "ippc";
0612 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
0613 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
0614 <&topckgen CLK_TOP_ETHIF_SEL>;
0615 clock-names = "sys_ck", "ref_ck";
0616 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
0617 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
0618 status = "disabled";
0619 };
0620
0621 u3phy0: t-phy@1a1c4000 {
0622 compatible = "mediatek,mt2701-tphy",
0623 "mediatek,generic-tphy-v1";
0624 reg = <0 0x1a1c4000 0 0x0700>;
0625 #address-cells = <2>;
0626 #size-cells = <2>;
0627 ranges;
0628 status = "disabled";
0629
0630 u2port0: usb-phy@1a1c4800 {
0631 reg = <0 0x1a1c4800 0 0x0100>;
0632 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
0633 clock-names = "ref";
0634 #phy-cells = <1>;
0635 status = "okay";
0636 };
0637
0638 u3port0: usb-phy@1a1c4900 {
0639 reg = <0 0x1a1c4900 0 0x0700>;
0640 clocks = <&clk26m>;
0641 clock-names = "ref";
0642 #phy-cells = <1>;
0643 status = "okay";
0644 };
0645 };
0646
0647 usb1: usb@1a240000 {
0648 compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci";
0649 reg = <0 0x1a240000 0 0x1000>,
0650 <0 0x1a244700 0 0x0100>;
0651 reg-names = "mac", "ippc";
0652 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
0653 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
0654 <&topckgen CLK_TOP_ETHIF_SEL>;
0655 clock-names = "sys_ck", "ref_ck";
0656 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
0657 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
0658 status = "disabled";
0659 };
0660
0661 u3phy1: t-phy@1a244000 {
0662 compatible = "mediatek,mt2701-tphy",
0663 "mediatek,generic-tphy-v1";
0664 reg = <0 0x1a244000 0 0x0700>;
0665 #address-cells = <2>;
0666 #size-cells = <2>;
0667 ranges;
0668 status = "disabled";
0669
0670 u2port1: usb-phy@1a244800 {
0671 reg = <0 0x1a244800 0 0x0100>;
0672 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
0673 clock-names = "ref";
0674 #phy-cells = <1>;
0675 status = "okay";
0676 };
0677
0678 u3port1: usb-phy@1a244900 {
0679 reg = <0 0x1a244900 0 0x0700>;
0680 clocks = <&clk26m>;
0681 clock-names = "ref";
0682 #phy-cells = <1>;
0683 status = "okay";
0684 };
0685 };
0686
0687 usb2: usb@11200000 {
0688 compatible = "mediatek,mt2701-musb",
0689 "mediatek,mtk-musb";
0690 reg = <0 0x11200000 0 0x1000>;
0691 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
0692 interrupt-names = "mc";
0693 phys = <&u2port2 PHY_TYPE_USB2>;
0694 dr_mode = "otg";
0695 clocks = <&pericfg CLK_PERI_USB0>,
0696 <&pericfg CLK_PERI_USB0_MCU>,
0697 <&pericfg CLK_PERI_USB_SLV>;
0698 clock-names = "main","mcu","univpll";
0699 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
0700 status = "disabled";
0701 };
0702
0703 u2phy0: t-phy@11210000 {
0704 compatible = "mediatek,mt2701-tphy",
0705 "mediatek,generic-tphy-v1";
0706 reg = <0 0x11210000 0 0x0800>;
0707 #address-cells = <2>;
0708 #size-cells = <2>;
0709 ranges;
0710 status = "okay";
0711
0712 u2port2: usb-phy@1a1c4800 {
0713 reg = <0 0x11210800 0 0x0100>;
0714 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
0715 clock-names = "ref";
0716 #phy-cells = <1>;
0717 status = "okay";
0718 };
0719 };
0720
0721 ethsys: syscon@1b000000 {
0722 compatible = "mediatek,mt2701-ethsys", "syscon";
0723 reg = <0 0x1b000000 0 0x1000>;
0724 #clock-cells = <1>;
0725 #reset-cells = <1>;
0726 };
0727
0728 eth: ethernet@1b100000 {
0729 compatible = "mediatek,mt2701-eth", "syscon";
0730 reg = <0 0x1b100000 0 0x20000>;
0731 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
0732 <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
0733 <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
0734 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
0735 <ðsys CLK_ETHSYS_ESW>,
0736 <ðsys CLK_ETHSYS_GP1>,
0737 <ðsys CLK_ETHSYS_GP2>,
0738 <&apmixedsys CLK_APMIXED_TRGPLL>;
0739 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
0740 resets = <ðsys MT2701_ETHSYS_FE_RST>,
0741 <ðsys MT2701_ETHSYS_GMAC_RST>,
0742 <ðsys MT2701_ETHSYS_PPE_RST>;
0743 reset-names = "fe", "gmac", "ppe";
0744 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
0745 mediatek,ethsys = <ðsys>;
0746 mediatek,pctl = <&syscfg_pctl_a>;
0747 #address-cells = <1>;
0748 #size-cells = <0>;
0749 status = "disabled";
0750 };
0751
0752 bdpsys: syscon@1c000000 {
0753 compatible = "mediatek,mt2701-bdpsys", "syscon";
0754 reg = <0 0x1c000000 0 0x1000>;
0755 #clock-cells = <1>;
0756 };
0757 };
