0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Copyright (c) 2020 thingy.jp.
0004 * Author: Daniel Palmer <daniel@thingy.jp>
0005 */
0006
0007 #include <dt-bindings/interrupt-controller/irq.h>
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/clock/mstar-msc313-mpll.h>
0010
0011 / {
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 interrupt-parent = <&gic>;
0015
0016 cpus: cpus {
0017 #address-cells = <1>;
0018 #size-cells = <0>;
0019
0020 cpu0: cpu@0 {
0021 device_type = "cpu";
0022 compatible = "arm,cortex-a7";
0023 reg = <0x0>;
0024 clocks = <&cpupll>;
0025 clock-names = "cpuclk";
0026 };
0027 };
0028
0029 arch_timer {
0030 compatible = "arm,armv7-timer";
0031 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
0032 | IRQ_TYPE_LEVEL_LOW)>,
0033 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)
0034 | IRQ_TYPE_LEVEL_LOW)>,
0035 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)
0036 | IRQ_TYPE_LEVEL_LOW)>,
0037 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)
0038 | IRQ_TYPE_LEVEL_LOW)>;
0039 /*
0040 * we shouldn't need this but the vendor
0041 * u-boot is broken
0042 */
0043 clock-frequency = <6000000>;
0044 arm,cpu-registers-not-fw-configured;
0045 };
0046
0047 pmu: pmu {
0048 compatible = "arm,cortex-a7-pmu";
0049 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0050 interrupt-affinity = <&cpu0>;
0051 };
0052
0053 clocks: clocks {
0054 xtal: xtal {
0055 #clock-cells = <0>;
0056 compatible = "fixed-clock";
0057 clock-frequency = <24000000>;
0058 };
0059
0060 rtc_xtal: rtc_xtal {
0061 #clock-cells = <0>;
0062 compatible = "fixed-clock";
0063 clock-frequency = <32768>;
0064 status = "disabled";
0065 };
0066
0067 xtal_div2: xtal_div2 {
0068 #clock-cells = <0>;
0069 compatible = "fixed-factor-clock";
0070 clocks = <&xtal>;
0071 clock-div = <2>;
0072 clock-mult = <1>;
0073 };
0074 };
0075
0076 soc: soc {
0077 compatible = "simple-bus";
0078 #address-cells = <1>;
0079 #size-cells = <1>;
0080 ranges = <0x16001000 0x16001000 0x00007000>,
0081 <0x1f000000 0x1f000000 0x00400000>,
0082 <0xa0000000 0xa0000000 0x20000>;
0083
0084 gic: interrupt-controller@16001000 {
0085 compatible = "arm,cortex-a7-gic";
0086 reg = <0x16001000 0x1000>,
0087 <0x16002000 0x2000>,
0088 <0x16004000 0x2000>,
0089 <0x16006000 0x2000>;
0090 #interrupt-cells = <3>;
0091 interrupt-controller;
0092 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2)
0093 | IRQ_TYPE_LEVEL_LOW)>;
0094 };
0095
0096 riu: bus@1f000000 {
0097 compatible = "simple-bus";
0098 reg = <0x1f000000 0x00400000>;
0099 #address-cells = <1>;
0100 #size-cells = <1>;
0101 ranges = <0x0 0x1f000000 0x00400000>;
0102
0103 pmsleep: syscon@1c00 {
0104 compatible = "mstar,msc313-pmsleep", "syscon";
0105 reg = <0x1c00 0x100>;
0106 };
0107
0108 reboot {
0109 compatible = "syscon-reboot";
0110 regmap = <&pmsleep>;
0111 offset = <0xb8>;
0112 mask = <0x79>;
0113 };
0114
0115 rtc@2400 {
0116 compatible = "mstar,msc313-rtc";
0117 reg = <0x2400 0x40>;
0118 clocks = <&xtal_div2>;
0119 interrupts-extended = <&intc_irq GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
0120 };
0121
0122 watchdog@6000 {
0123 compatible = "mstar,msc313e-wdt";
0124 reg = <0x6000 0x1f>;
0125 clocks = <&xtal_div2>;
0126 };
0127
0128
0129 intc_fiq: interrupt-controller@201310 {
0130 compatible = "mstar,mst-intc";
0131 reg = <0x201310 0x40>;
0132 #interrupt-cells = <3>;
0133 interrupt-controller;
0134 interrupt-parent = <&gic>;
0135 mstar,irqs-map-range = <96 127>;
0136 };
0137
0138 intc_irq: interrupt-controller@201350 {
0139 compatible = "mstar,mst-intc";
0140 reg = <0x201350 0x40>;
0141 #interrupt-cells = <3>;
0142 interrupt-controller;
0143 interrupt-parent = <&gic>;
0144 mstar,irqs-map-range = <32 95>;
0145 mstar,intc-no-eoi;
0146 };
0147
0148 l3bridge: l3bridge@204400 {
0149 compatible = "mstar,l3bridge";
0150 reg = <0x204400 0x200>;
0151 };
0152
0153 mpll: mpll@206000 {
0154 compatible = "mstar,msc313-mpll";
0155 #clock-cells = <1>;
0156 reg = <0x206000 0x200>;
0157 clocks = <&xtal>;
0158 };
0159
0160 cpupll: cpupll@206400 {
0161 compatible = "mstar,msc313-cpupll";
0162 reg = <0x206400 0x200>;
0163 #clock-cells = <0>;
0164 clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
0165 };
0166
0167 gpio: gpio@207800 {
0168 #gpio-cells = <2>;
0169 reg = <0x207800 0x200>;
0170 gpio-controller;
0171 #interrupt-cells = <2>;
0172 interrupt-controller;
0173 interrupt-parent = <&intc_fiq>;
0174 status = "disabled";
0175 };
0176
0177 pm_uart: uart@221000 {
0178 compatible = "ns16550a";
0179 reg = <0x221000 0x100>;
0180 reg-shift = <3>;
0181 interrupts-extended = <&intc_irq GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0182 clock-frequency = <172000000>;
0183 status = "disabled";
0184 };
0185 };
0186
0187 imi: sram@a0000000 {
0188 compatible = "mmio-sram";
0189 reg = <0xa0000000 0x10000>;
0190 };
0191 };
0192 };
