0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* moxart.dtsi - Device Tree Include file for MOXA ART family SoC
0003 *
0004 * Copyright (C) 2013 Jonas Jensen <jonas.jensen@gmail.com>
0005 */
0006
0007 #include <dt-bindings/interrupt-controller/irq.h>
0008
0009 / {
0010 #address-cells = <1>;
0011 #size-cells = <1>;
0012 compatible = "moxa,moxart";
0013 model = "MOXART";
0014 interrupt-parent = <&intc>;
0015
0016 cpus {
0017 #address-cells = <1>;
0018 #size-cells = <0>;
0019
0020 cpu@0 {
0021 device_type = "cpu";
0022 compatible = "faraday,fa526";
0023 reg = <0>;
0024 };
0025 };
0026
0027 clocks {
0028 #address-cells = <1>;
0029 #size-cells = <0>;
0030 };
0031
0032 soc {
0033 compatible = "simple-bus";
0034 #address-cells = <1>;
0035 #size-cells = <1>;
0036 reg = <0x90000000 0x10000000>;
0037 ranges;
0038
0039 intc: interrupt-controller@98800000 {
0040 compatible = "moxa,moxart-ic", "faraday,ftintc010";
0041 reg = <0x98800000 0x100>;
0042 interrupt-controller;
0043 #interrupt-cells = <2>;
0044 interrupt-mask = <0x00080000>;
0045 };
0046
0047 clk_pll: clk_pll@98100000 {
0048 compatible = "moxa,moxart-pll-clock";
0049 #clock-cells = <0>;
0050 reg = <0x98100000 0x34>;
0051 };
0052
0053 clk_apb: clk_apb@98100000 {
0054 compatible = "moxa,moxart-apb-clock";
0055 #clock-cells = <0>;
0056 reg = <0x98100000 0x34>;
0057 clocks = <&clk_pll>;
0058 };
0059
0060 timer: timer@98400000 {
0061 compatible = "moxa,moxart-timer", "faraday,fttmr010";
0062 reg = <0x98400000 0x42>;
0063 interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
0064 clocks = <&clk_apb>;
0065 clock-names = "PCLK";
0066 };
0067
0068 gpio: gpio@98700000 {
0069 gpio-controller;
0070 #gpio-cells = <2>;
0071 compatible = "moxa,moxart-gpio", "faraday,ftgpio010";
0072 reg = <0x98700000 0x100>;
0073 };
0074
0075 rtc: rtc {
0076 compatible = "moxa,moxart-rtc";
0077 gpio-rtc-sclk = <&gpio 5 0>;
0078 gpio-rtc-data = <&gpio 6 0>;
0079 gpio-rtc-reset = <&gpio 7 0>;
0080 };
0081
0082 dma: dma@90500000 {
0083 compatible = "moxa,moxart-dma";
0084 reg = <0x90500080 0x40>;
0085 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
0086 #dma-cells = <1>;
0087 };
0088
0089 watchdog: watchdog@98500000 {
0090 compatible = "moxa,moxart-watchdog", "faraday,ftwdt010";
0091 reg = <0x98500000 0x10>;
0092 clocks = <&clk_apb>;
0093 clock-names = "PCLK";
0094 };
0095
0096 mmc: mmc@98e00000 {
0097 compatible = "moxa,moxart-mmc";
0098 reg = <0x98e00000 0x5C>;
0099 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
0100 clocks = <&clk_apb>;
0101 dmas = <&dma 5>,
0102 <&dma 5>;
0103 dma-names = "tx", "rx";
0104 status = "disabled";
0105 };
0106
0107 mdio0: mdio@90900090 {
0108 compatible = "moxa,moxart-mdio";
0109 reg = <0x90900090 0x8>;
0110 #address-cells = <1>;
0111 #size-cells = <0>;
0112 status = "disabled";
0113 };
0114
0115 mdio1: mdio@92000090 {
0116 compatible = "moxa,moxart-mdio";
0117 reg = <0x92000090 0x8>;
0118 #address-cells = <1>;
0119 #size-cells = <0>;
0120 status = "disabled";
0121 };
0122
0123 mac0: mac@90900000 {
0124 compatible = "moxa,moxart-mac";
0125 reg = <0x90900000 0x90>;
0126 interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
0127 phy-handle = <ðphy0>;
0128 phy-mode = "mii";
0129 status = "disabled";
0130 };
0131
0132 mac1: mac@92000000 {
0133 compatible = "moxa,moxart-mac";
0134 reg = <0x92000000 0x90>;
0135 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
0136 phy-handle = <ðphy1>;
0137 phy-mode = "mii";
0138 status = "disabled";
0139 };
0140
0141 uart0: uart@98200000 {
0142 compatible = "ns16550a";
0143 reg = <0x98200000 0x20>;
0144 interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
0145 reg-shift = <2>;
0146 reg-io-width = <4>;
0147 clock-frequency = <14745600>;
0148 status = "disabled";
0149 };
0150 };
0151 };
