0001 // SPDX-License-Identifier: GPL-2.0+ OR MIT
0002 /*
0003 * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
0004 */
0005
0006 #include <dt-bindings/clock/marvell,mmp2.h>
0007 #include <dt-bindings/power/marvell,mmp2.h>
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009
0010 / {
0011 #address-cells = <1>;
0012 #size-cells = <1>;
0013
0014 cpus {
0015 #address-cells = <1>;
0016 #size-cells = <0>;
0017 enable-method = "marvell,mmp3-smp";
0018
0019 cpu@0 {
0020 compatible = "marvell,pj4b";
0021 device_type = "cpu";
0022 next-level-cache = <&l2>;
0023 reg = <0>;
0024 };
0025
0026 cpu@1 {
0027 compatible = "marvell,pj4b";
0028 device_type = "cpu";
0029 next-level-cache = <&l2>;
0030 reg = <1>;
0031 };
0032 };
0033
0034 soc {
0035 #address-cells = <1>;
0036 #size-cells = <1>;
0037 compatible = "simple-bus";
0038 interrupt-parent = <&gic>;
0039 ranges;
0040
0041 axi@d4200000 {
0042 compatible = "simple-bus";
0043 #address-cells = <1>;
0044 #size-cells = <1>;
0045 reg = <0xd4200000 0x00200000>;
0046 ranges;
0047
0048 interrupt-controller@d4282000 {
0049 compatible = "marvell,mmp3-intc";
0050 interrupt-controller;
0051 #interrupt-cells = <1>;
0052 reg = <0xd4282000 0x1000>,
0053 <0xd4284000 0x100>;
0054 mrvl,intc-nr-irqs = <64>;
0055 };
0056
0057 pmic_mux: interrupt-controller@d4282150 {
0058 compatible = "mrvl,mmp2-mux-intc";
0059 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0060 interrupt-controller;
0061 #interrupt-cells = <1>;
0062 reg = <0x150 0x4>, <0x168 0x4>;
0063 reg-names = "mux status", "mux mask";
0064 mrvl,intc-nr-irqs = <4>;
0065 };
0066
0067 rtc_mux: interrupt-controller@d4282154 {
0068 compatible = "mrvl,mmp2-mux-intc";
0069 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0070 interrupt-controller;
0071 #interrupt-cells = <1>;
0072 reg = <0x154 0x4>, <0x16c 0x4>;
0073 reg-names = "mux status", "mux mask";
0074 mrvl,intc-nr-irqs = <2>;
0075 };
0076
0077 hsi3_mux: interrupt-controller@d42821bc {
0078 compatible = "mrvl,mmp2-mux-intc";
0079 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0080 interrupt-controller;
0081 #interrupt-cells = <1>;
0082 reg = <0x1bc 0x4>, <0x1a4 0x4>;
0083 reg-names = "mux status", "mux mask";
0084 mrvl,intc-nr-irqs = <3>;
0085 };
0086
0087 gpu_mux: interrupt-controller@d42821c0 {
0088 compatible = "mrvl,mmp2-mux-intc";
0089 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0090 interrupt-controller;
0091 #interrupt-cells = <1>;
0092 reg = <0x1c0 0x4>, <0x1a8 0x4>;
0093 reg-names = "mux status", "mux mask";
0094 mrvl,intc-nr-irqs = <3>;
0095 };
0096
0097 twsi_mux: interrupt-controller@d4282158 {
0098 compatible = "mrvl,mmp2-mux-intc";
0099 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0100 interrupt-controller;
0101 #interrupt-cells = <1>;
0102 reg = <0x158 0x4>, <0x170 0x4>;
0103 reg-names = "mux status", "mux mask";
0104 mrvl,intc-nr-irqs = <5>;
0105 };
0106
0107 hsi2_mux: interrupt-controller@d42821c4 {
0108 compatible = "mrvl,mmp2-mux-intc";
0109 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0110 interrupt-controller;
0111 #interrupt-cells = <1>;
0112 reg = <0x1c4 0x4>, <0x1ac 0x4>;
0113 reg-names = "mux status", "mux mask";
0114 mrvl,intc-nr-irqs = <2>;
0115 };
0116
0117 dxo_mux: interrupt-controller@d42821c8 {
0118 compatible = "mrvl,mmp2-mux-intc";
0119 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0120 interrupt-controller;
0121 #interrupt-cells = <1>;
0122 reg = <0x1c8 0x4>, <0x1b0 0x4>;
0123 reg-names = "mux status", "mux mask";
0124 mrvl,intc-nr-irqs = <2>;
0125 };
0126
0127 misc1_mux: interrupt-controller@d428215c {
0128 compatible = "mrvl,mmp2-mux-intc";
0129 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0130 interrupt-controller;
0131 #interrupt-cells = <1>;
0132 reg = <0x15c 0x4>, <0x174 0x4>;
0133 reg-names = "mux status", "mux mask";
0134 mrvl,intc-nr-irqs = <31>;
0135 };
0136
0137 ci_mux: interrupt-controller@d42821cc {
0138 compatible = "mrvl,mmp2-mux-intc";
0139 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0140 interrupt-controller;
0141 #interrupt-cells = <1>;
0142 reg = <0x1cc 0x4>, <0x1b4 0x4>;
0143 reg-names = "mux status", "mux mask";
0144 mrvl,intc-nr-irqs = <2>;
0145 };
0146
0147 ssp_mux: interrupt-controller@d4282160 {
0148 compatible = "mrvl,mmp2-mux-intc";
0149 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0150 interrupt-controller;
0151 #interrupt-cells = <1>;
0152 reg = <0x160 0x4>, <0x178 0x4>;
0153 reg-names = "mux status", "mux mask";
0154 mrvl,intc-nr-irqs = <2>;
0155 };
0156
0157 hsi1_mux: interrupt-controller@d4282184 {
0158 compatible = "mrvl,mmp2-mux-intc";
0159 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0160 interrupt-controller;
0161 #interrupt-cells = <1>;
0162 reg = <0x184 0x4>, <0x17c 0x4>;
0163 reg-names = "mux status", "mux mask";
0164 mrvl,intc-nr-irqs = <4>;
0165 };
0166
0167 misc2_mux: interrupt-controller@d4282188 {
0168 compatible = "mrvl,mmp2-mux-intc";
0169 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0170 interrupt-controller;
0171 #interrupt-cells = <1>;
0172 reg = <0x188 0x4>, <0x180 0x4>;
0173 reg-names = "mux status", "mux mask";
0174 mrvl,intc-nr-irqs = <20>;
0175 };
0176
0177 hsi0_mux: interrupt-controller@d42821d0 {
0178 compatible = "mrvl,mmp2-mux-intc";
0179 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0180 interrupt-controller;
0181 #interrupt-cells = <1>;
0182 reg = <0x1d0 0x4>, <0x1b8 0x4>;
0183 reg-names = "mux status", "mux mask";
0184 mrvl,intc-nr-irqs = <5>;
0185 };
0186
0187 usb_otg_phy0: usb-phy@d4207000 {
0188 compatible = "marvell,mmp3-usb-phy";
0189 reg = <0xd4207000 0x40>;
0190 #phy-cells = <0>;
0191 status = "disabled";
0192 };
0193
0194 usb_otg0: usb@d4208000 {
0195 compatible = "marvell,pxau2o-ehci";
0196 reg = <0xd4208000 0x200>;
0197 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
0198 clocks = <&soc_clocks MMP2_CLK_USB>;
0199 clock-names = "USBCLK";
0200 phys = <&usb_otg_phy0>;
0201 phy-names = "usb";
0202 status = "disabled";
0203 };
0204
0205 hsic_phy0: usb-phy@f0001800 {
0206 compatible = "marvell,mmp3-hsic-phy";
0207 reg = <0xf0001800 0x40>;
0208 #phy-cells = <0>;
0209 status = "disabled";
0210 };
0211
0212 hsic0: usb@f0001000 {
0213 compatible = "marvell,pxau2o-ehci";
0214 reg = <0xf0001000 0x200>;
0215 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0216 clocks = <&soc_clocks MMP2_CLK_USBHSIC0>;
0217 clock-names = "USBCLK";
0218 phys = <&hsic_phy0>;
0219 phy-names = "usb";
0220 phy_type = "hsic";
0221 #address-cells = <0x01>;
0222 #size-cells = <0x00>;
0223 status = "disabled";
0224 };
0225
0226 hsic_phy1: usb-phy@f0002800 {
0227 compatible = "marvell,mmp3-hsic-phy";
0228 reg = <0xf0002800 0x40>;
0229 #phy-cells = <0>;
0230 status = "disabled";
0231 };
0232
0233 hsic1: usb@f0002000 {
0234 compatible = "marvell,pxau2o-ehci";
0235 reg = <0xf0002000 0x200>;
0236 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0237 clocks = <&soc_clocks MMP2_CLK_USBHSIC1>;
0238 clock-names = "USBCLK";
0239 phys = <&hsic_phy1>;
0240 phy-names = "usb";
0241 phy_type = "hsic";
0242 #address-cells = <0x01>;
0243 #size-cells = <0x00>;
0244 status = "disabled";
0245 };
0246
0247 mmc1: mmc@d4280000 {
0248 compatible = "mrvl,pxav3-mmc";
0249 reg = <0xd4280000 0x120>;
0250 clocks = <&soc_clocks MMP2_CLK_SDH0>;
0251 clock-names = "io";
0252 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0253 status = "disabled";
0254 };
0255
0256 mmc2: mmc@d4280800 {
0257 compatible = "mrvl,pxav3-mmc";
0258 reg = <0xd4280800 0x120>;
0259 clocks = <&soc_clocks MMP2_CLK_SDH1>;
0260 clock-names = "io";
0261 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
0262 status = "disabled";
0263 };
0264
0265 mmc3: mmc@d4281000 {
0266 compatible = "mrvl,pxav3-mmc";
0267 reg = <0xd4281000 0x120>;
0268 clocks = <&soc_clocks MMP2_CLK_SDH2>;
0269 clock-names = "io";
0270 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0271 status = "disabled";
0272 };
0273
0274 mmc4: mmc@d4281800 {
0275 compatible = "mrvl,pxav3-mmc";
0276 reg = <0xd4281800 0x120>;
0277 clocks = <&soc_clocks MMP2_CLK_SDH3>;
0278 clock-names = "io";
0279 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
0280 status = "disabled";
0281 };
0282
0283 mmc5: mmc@d4217000 {
0284 compatible = "mrvl,pxav3-mmc";
0285 reg = <0xd4217000 0x120>;
0286 clocks = <&soc_clocks MMP3_CLK_SDH4>;
0287 clock-names = "io";
0288 interrupt-parent = <&hsi1_mux>;
0289 interrupts = <0>;
0290 status = "disabled";
0291 };
0292
0293 camera0: camera@d420a000 {
0294 compatible = "marvell,mmp2-ccic";
0295 reg = <0xd420a000 0x800>;
0296 interrupts = <1>;
0297 interrupt-parent = <&ci_mux>;
0298 clocks = <&soc_clocks MMP2_CLK_CCIC0>;
0299 clock-names = "axi";
0300 power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
0301 #clock-cells = <0>;
0302 clock-output-names = "mclk";
0303 status = "disabled";
0304 };
0305
0306 camera1: camera@d420a800 {
0307 compatible = "marvell,mmp2-ccic";
0308 reg = <0xd420a800 0x800>;
0309 interrupts = <2>;
0310 interrupt-parent = <&ci_mux>;
0311 clocks = <&soc_clocks MMP2_CLK_CCIC1>;
0312 clock-names = "axi";
0313 power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
0314 #clock-cells = <0>;
0315 clock-output-names = "mclk";
0316 status = "disabled";
0317 };
0318
0319 gpu_3d: gpu@d420d000 {
0320 compatible = "vivante,gc";
0321 reg = <0xd420d000 0x2000>;
0322 interrupt-parent = <&gpu_mux>;
0323 interrupts = <0>;
0324 status = "disabled";
0325 clocks = <&soc_clocks MMP3_CLK_GPU_3D>,
0326 <&soc_clocks MMP3_CLK_GPU_BUS>;
0327 clock-names = "core", "bus";
0328 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
0329 };
0330
0331 gpu_2d: gpu@d420f000 {
0332 compatible = "vivante,gc";
0333 reg = <0xd420f000 0x2000>;
0334 interrupt-parent = <&gpu_mux>;
0335 interrupts = <2>;
0336 status = "disabled";
0337 clocks = <&soc_clocks MMP3_CLK_GPU_2D>,
0338 <&soc_clocks MMP3_CLK_GPU_BUS>;
0339 clock-names = "core", "bus";
0340 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
0341 };
0342 };
0343
0344 apb@d4000000 {
0345 compatible = "simple-bus";
0346 #address-cells = <1>;
0347 #size-cells = <1>;
0348 reg = <0xd4000000 0x00200000>;
0349 ranges;
0350
0351 timer: timer@d4014000 {
0352 compatible = "mrvl,mmp-timer";
0353 reg = <0xd4014000 0x100>;
0354 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0355 clocks = <&soc_clocks MMP2_CLK_TIMER>;
0356 };
0357
0358 uart1: serial@d4030000 {
0359 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
0360 reg = <0xd4030000 0x1000>;
0361 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0362 clocks = <&soc_clocks MMP2_CLK_UART0>;
0363 resets = <&soc_clocks MMP2_CLK_UART0>;
0364 reg-shift = <2>;
0365 status = "disabled";
0366 };
0367
0368 uart2: serial@d4017000 {
0369 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
0370 reg = <0xd4017000 0x1000>;
0371 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0372 clocks = <&soc_clocks MMP2_CLK_UART1>;
0373 resets = <&soc_clocks MMP2_CLK_UART1>;
0374 reg-shift = <2>;
0375 status = "disabled";
0376 };
0377
0378 uart3: serial@d4018000 {
0379 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
0380 reg = <0xd4018000 0x1000>;
0381 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0382 clocks = <&soc_clocks MMP2_CLK_UART2>;
0383 resets = <&soc_clocks MMP2_CLK_UART2>;
0384 reg-shift = <2>;
0385 status = "disabled";
0386 };
0387
0388 uart4: serial@d4016000 {
0389 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
0390 reg = <0xd4016000 0x1000>;
0391 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0392 clocks = <&soc_clocks MMP2_CLK_UART3>;
0393 resets = <&soc_clocks MMP2_CLK_UART3>;
0394 reg-shift = <2>;
0395 status = "disabled";
0396 };
0397
0398 gpio: gpio@d4019000 {
0399 compatible = "marvell,mmp2-gpio";
0400 #address-cells = <1>;
0401 #size-cells = <1>;
0402 reg = <0xd4019000 0x1000>;
0403 gpio-controller;
0404 #gpio-cells = <2>;
0405 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0406 interrupt-names = "gpio_mux";
0407 clocks = <&soc_clocks MMP2_CLK_GPIO>;
0408 resets = <&soc_clocks MMP2_CLK_GPIO>;
0409 interrupt-controller;
0410 #interrupt-cells = <2>;
0411 ranges;
0412
0413 gcb0: gpio@d4019000 {
0414 reg = <0xd4019000 0x4>;
0415 };
0416
0417 gcb1: gpio@d4019004 {
0418 reg = <0xd4019004 0x4>;
0419 };
0420
0421 gcb2: gpio@d4019008 {
0422 reg = <0xd4019008 0x4>;
0423 };
0424
0425 gcb3: gpio@d4019100 {
0426 reg = <0xd4019100 0x4>;
0427 };
0428
0429 gcb4: gpio@d4019104 {
0430 reg = <0xd4019104 0x4>;
0431 };
0432
0433 gcb5: gpio@d4019108 {
0434 reg = <0xd4019108 0x4>;
0435 };
0436 };
0437
0438 twsi1: i2c@d4011000 {
0439 compatible = "mrvl,mmp-twsi";
0440 reg = <0xd4011000 0x70>;
0441 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0442 clocks = <&soc_clocks MMP2_CLK_TWSI0>;
0443 resets = <&soc_clocks MMP2_CLK_TWSI0>;
0444 #address-cells = <1>;
0445 #size-cells = <0>;
0446 mrvl,i2c-fast-mode;
0447 status = "disabled";
0448 };
0449
0450 twsi2: i2c@d4031000 {
0451 compatible = "mrvl,mmp-twsi";
0452 reg = <0xd4031000 0x70>;
0453 interrupt-parent = <&twsi_mux>;
0454 interrupts = <0>;
0455 clocks = <&soc_clocks MMP2_CLK_TWSI1>;
0456 resets = <&soc_clocks MMP2_CLK_TWSI1>;
0457 #address-cells = <1>;
0458 #size-cells = <0>;
0459 status = "disabled";
0460 };
0461
0462 twsi3: i2c@d4032000 {
0463 compatible = "mrvl,mmp-twsi";
0464 reg = <0xd4032000 0x70>;
0465 interrupt-parent = <&twsi_mux>;
0466 interrupts = <1>;
0467 clocks = <&soc_clocks MMP2_CLK_TWSI2>;
0468 resets = <&soc_clocks MMP2_CLK_TWSI2>;
0469 #address-cells = <1>;
0470 #size-cells = <0>;
0471 status = "disabled";
0472 };
0473
0474 twsi4: i2c@d4033000 {
0475 compatible = "mrvl,mmp-twsi";
0476 reg = <0xd4033000 0x70>;
0477 interrupt-parent = <&twsi_mux>;
0478 interrupts = <2>;
0479 clocks = <&soc_clocks MMP2_CLK_TWSI3>;
0480 resets = <&soc_clocks MMP2_CLK_TWSI3>;
0481 #address-cells = <1>;
0482 #size-cells = <0>;
0483 status = "disabled";
0484 };
0485
0486
0487 twsi5: i2c@d4033800 {
0488 compatible = "mrvl,mmp-twsi";
0489 reg = <0xd4033800 0x70>;
0490 interrupt-parent = <&twsi_mux>;
0491 interrupts = <3>;
0492 clocks = <&soc_clocks MMP2_CLK_TWSI4>;
0493 resets = <&soc_clocks MMP2_CLK_TWSI4>;
0494 #address-cells = <1>;
0495 #size-cells = <0>;
0496 status = "disabled";
0497 };
0498
0499 twsi6: i2c@d4034000 {
0500 compatible = "mrvl,mmp-twsi";
0501 reg = <0xd4034000 0x70>;
0502 interrupt-parent = <&twsi_mux>;
0503 interrupts = <4>;
0504 clocks = <&soc_clocks MMP2_CLK_TWSI5>;
0505 resets = <&soc_clocks MMP2_CLK_TWSI5>;
0506 #address-cells = <1>;
0507 #size-cells = <0>;
0508 status = "disabled";
0509 };
0510
0511 rtc: rtc@d4010000 {
0512 compatible = "mrvl,mmp-rtc";
0513 reg = <0xd4010000 0x1000>;
0514 interrupts = <1>, <0>;
0515 interrupt-names = "rtc 1Hz", "rtc alarm";
0516 interrupt-parent = <&rtc_mux>;
0517 clocks = <&soc_clocks MMP2_CLK_RTC>;
0518 resets = <&soc_clocks MMP2_CLK_RTC>;
0519 status = "disabled";
0520 };
0521
0522 ssp1: spi@d4035000 {
0523 compatible = "marvell,mmp2-ssp";
0524 reg = <0xd4035000 0x1000>;
0525 clocks = <&soc_clocks MMP2_CLK_SSP0>;
0526 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0527 #address-cells = <1>;
0528 #size-cells = <0>;
0529 status = "disabled";
0530 };
0531
0532 ssp2: spi@d4036000 {
0533 compatible = "marvell,mmp2-ssp";
0534 reg = <0xd4036000 0x1000>;
0535 clocks = <&soc_clocks MMP2_CLK_SSP1>;
0536 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0537 #address-cells = <1>;
0538 #size-cells = <0>;
0539 status = "disabled";
0540 };
0541
0542 ssp3: spi@d4037000 {
0543 compatible = "marvell,mmp2-ssp";
0544 reg = <0xd4037000 0x1000>;
0545 clocks = <&soc_clocks MMP2_CLK_SSP2>;
0546 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0547 #address-cells = <1>;
0548 #size-cells = <0>;
0549 status = "disabled";
0550 };
0551
0552 ssp4: spi@d4039000 {
0553 compatible = "marvell,mmp2-ssp";
0554 reg = <0xd4039000 0x1000>;
0555 clocks = <&soc_clocks MMP2_CLK_SSP3>;
0556 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0557 #address-cells = <1>;
0558 #size-cells = <0>;
0559 status = "disabled";
0560 };
0561 };
0562
0563 l2: cache-controller@d0020000 {
0564 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
0565 reg = <0xd0020000 0x1000>;
0566 cache-unified;
0567 cache-level = <2>;
0568 };
0569
0570 soc_clocks: clocks@d4050000 {
0571 compatible = "marvell,mmp3-clock";
0572 reg = <0xd4050000 0x2000>,
0573 <0xd4282800 0x400>,
0574 <0xd4015000 0x1000>;
0575 reg-names = "mpmu", "apmu", "apbc";
0576 #clock-cells = <1>;
0577 #reset-cells = <1>;
0578 #power-domain-cells = <1>;
0579 };
0580
0581 snoop-control-unit@e0000000 {
0582 compatible = "arm,arm11mp-scu";
0583 reg = <0xe0000000 0x100>;
0584 };
0585
0586 gic: interrupt-controller@e0001000 {
0587 compatible = "arm,arm11mp-gic";
0588 interrupt-controller;
0589 #interrupt-cells = <3>;
0590 reg = <0xe0001000 0x1000>,
0591 <0xe0000100 0x100>;
0592 };
0593
0594 local-timer@e0000600 {
0595 compatible = "arm,arm11mp-twd-timer";
0596 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
0597 IRQ_TYPE_EDGE_RISING)>;
0598 reg = <0xe0000600 0x20>;
0599 };
0600
0601 watchdog@e0000620 {
0602 compatible = "arm,arm11mp-twd-wdt";
0603 reg = <0xe0000620 0x20>;
0604 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
0605 IRQ_TYPE_EDGE_RISING)>;
0606 };
0607 };
0608 };
