0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2012 Marvell Technology Group Ltd.
0004 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
0005 */
0006
0007 #include <dt-bindings/clock/marvell,mmp2.h>
0008 #include <dt-bindings/power/marvell,mmp2.h>
0009 #include <dt-bindings/clock/marvell,mmp2-audio.h>
0010
0011 / {
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014
0015 aliases {
0016 serial0 = &uart1;
0017 serial1 = &uart2;
0018 serial2 = &uart3;
0019 serial3 = &uart4;
0020 i2c0 = &twsi1;
0021 i2c1 = &twsi2;
0022 };
0023
0024 soc {
0025 #address-cells = <1>;
0026 #size-cells = <1>;
0027 compatible = "simple-bus";
0028 interrupt-parent = <&intc>;
0029 ranges;
0030
0031 L2: l2-cache {
0032 compatible = "marvell,tauros2-cache";
0033 marvell,tauros2-cache-features = <0x3>;
0034 };
0035
0036 axi@d4200000 { /* AXI */
0037 compatible = "mrvl,axi-bus", "simple-bus";
0038 #address-cells = <1>;
0039 #size-cells = <1>;
0040 reg = <0xd4200000 0x00200000>;
0041 ranges;
0042
0043 gpu: gpu@d420d000 {
0044 compatible = "vivante,gc";
0045 reg = <0xd420d000 0x4000>;
0046 interrupts = <8>;
0047 status = "disabled";
0048 clocks = <&soc_clocks MMP2_CLK_GPU_3D>,
0049 <&soc_clocks MMP2_CLK_GPU_BUS>;
0050 clock-names = "core", "bus";
0051 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
0052 };
0053
0054 intc: interrupt-controller@d4282000 {
0055 compatible = "mrvl,mmp2-intc";
0056 interrupt-controller;
0057 #interrupt-cells = <1>;
0058 reg = <0xd4282000 0x1000>;
0059 mrvl,intc-nr-irqs = <64>;
0060 };
0061
0062 intcmux4: interrupt-controller@d4282150 {
0063 compatible = "mrvl,mmp2-mux-intc";
0064 interrupts = <4>;
0065 interrupt-controller;
0066 #interrupt-cells = <1>;
0067 reg = <0x150 0x4>, <0x168 0x4>;
0068 reg-names = "mux status", "mux mask";
0069 mrvl,intc-nr-irqs = <2>;
0070 };
0071
0072 intcmux5: interrupt-controller@d4282154 {
0073 compatible = "mrvl,mmp2-mux-intc";
0074 interrupts = <5>;
0075 interrupt-controller;
0076 #interrupt-cells = <1>;
0077 reg = <0x154 0x4>, <0x16c 0x4>;
0078 reg-names = "mux status", "mux mask";
0079 mrvl,intc-nr-irqs = <2>;
0080 mrvl,clr-mfp-irq = <1>;
0081 };
0082
0083 intcmux9: interrupt-controller@d4282180 {
0084 compatible = "mrvl,mmp2-mux-intc";
0085 interrupts = <9>;
0086 interrupt-controller;
0087 #interrupt-cells = <1>;
0088 reg = <0x180 0x4>, <0x17c 0x4>;
0089 reg-names = "mux status", "mux mask";
0090 mrvl,intc-nr-irqs = <3>;
0091 };
0092
0093 intcmux17: interrupt-controller@d4282158 {
0094 compatible = "mrvl,mmp2-mux-intc";
0095 interrupts = <17>;
0096 interrupt-controller;
0097 #interrupt-cells = <1>;
0098 reg = <0x158 0x4>, <0x170 0x4>;
0099 reg-names = "mux status", "mux mask";
0100 mrvl,intc-nr-irqs = <5>;
0101 };
0102
0103 intcmux35: interrupt-controller@d428215c {
0104 compatible = "mrvl,mmp2-mux-intc";
0105 interrupts = <35>;
0106 interrupt-controller;
0107 #interrupt-cells = <1>;
0108 reg = <0x15c 0x4>, <0x174 0x4>;
0109 reg-names = "mux status", "mux mask";
0110 mrvl,intc-nr-irqs = <15>;
0111 };
0112
0113 intcmux51: interrupt-controller@d4282160 {
0114 compatible = "mrvl,mmp2-mux-intc";
0115 interrupts = <51>;
0116 interrupt-controller;
0117 #interrupt-cells = <1>;
0118 reg = <0x160 0x4>, <0x178 0x4>;
0119 reg-names = "mux status", "mux mask";
0120 mrvl,intc-nr-irqs = <2>;
0121 };
0122
0123 intcmux55: interrupt-controller@d4282188 {
0124 compatible = "mrvl,mmp2-mux-intc";
0125 interrupts = <55>;
0126 interrupt-controller;
0127 #interrupt-cells = <1>;
0128 reg = <0x188 0x4>, <0x184 0x4>;
0129 reg-names = "mux status", "mux mask";
0130 mrvl,intc-nr-irqs = <2>;
0131 };
0132
0133 usb_phy0: usb-phy@d4207000 {
0134 compatible = "marvell,mmp2-usb-phy";
0135 reg = <0xd4207000 0x40>;
0136 #phy-cells = <0>;
0137 status = "disabled";
0138 };
0139
0140 usb_otg0: usb-otg@d4208000 {
0141 compatible = "marvell,pxau2o-ehci";
0142 reg = <0xd4208000 0x200>;
0143 interrupts = <44>;
0144 clocks = <&soc_clocks MMP2_CLK_USB>;
0145 clock-names = "USBCLK";
0146 phys = <&usb_phy0>;
0147 phy-names = "usb";
0148 status = "disabled";
0149 };
0150
0151 mmc1: mmc@d4280000 {
0152 compatible = "mrvl,pxav3-mmc";
0153 reg = <0xd4280000 0x120>;
0154 clocks = <&soc_clocks MMP2_CLK_SDH0>;
0155 clock-names = "io";
0156 interrupts = <39>;
0157 status = "disabled";
0158 };
0159
0160 mmc2: mmc@d4280800 {
0161 compatible = "mrvl,pxav3-mmc";
0162 reg = <0xd4280800 0x120>;
0163 clocks = <&soc_clocks MMP2_CLK_SDH1>;
0164 clock-names = "io";
0165 interrupts = <52>;
0166 status = "disabled";
0167 };
0168
0169 mmc3: mmc@d4281000 {
0170 compatible = "mrvl,pxav3-mmc";
0171 reg = <0xd4281000 0x120>;
0172 clocks = <&soc_clocks MMP2_CLK_SDH2>;
0173 clock-names = "io";
0174 interrupts = <53>;
0175 status = "disabled";
0176 };
0177
0178 mmc4: mmc@d4281800 {
0179 compatible = "mrvl,pxav3-mmc";
0180 reg = <0xd4281800 0x120>;
0181 clocks = <&soc_clocks MMP2_CLK_SDH3>;
0182 clock-names = "io";
0183 interrupts = <54>;
0184 status = "disabled";
0185 };
0186
0187 camera0: camera@d420a000 {
0188 compatible = "marvell,mmp2-ccic";
0189 reg = <0xd420a000 0x800>;
0190 interrupts = <42>;
0191 clocks = <&soc_clocks MMP2_CLK_CCIC0>;
0192 clock-names = "axi";
0193 #clock-cells = <0>;
0194 clock-output-names = "mclk";
0195 status = "disabled";
0196 };
0197
0198 camera1: camera@d420a800 {
0199 compatible = "marvell,mmp2-ccic";
0200 reg = <0xd420a800 0x800>;
0201 interrupts = <30>;
0202 clocks = <&soc_clocks MMP2_CLK_CCIC1>;
0203 clock-names = "axi";
0204 #clock-cells = <0>;
0205 clock-output-names = "mclk";
0206 status = "disabled";
0207 };
0208
0209 adma0: dma-controller@d42a0800 {
0210 compatible = "marvell,adma-1.0";
0211 reg = <0xd42a0800 0x100>;
0212 interrupts = <48>;
0213 #dma-cells = <1>;
0214 asram = <&asram>;
0215 iram = <&asram>;
0216 status = "disabled";
0217 };
0218
0219 adma1: dma-controller@d42a0900 {
0220 compatible = "marvell,adma-1.0";
0221 reg = <0xd42a0900 0x100>;
0222 interrupts = <48>;
0223 #dma-cells = <1>;
0224 status = "disabled";
0225 };
0226
0227 audio_clk: clocks@d42a0c30 {
0228 compatible = "marvell,mmp2-audio-clock";
0229 reg = <0xd42a0c30 0x10>;
0230 clock-names = "audio", "vctcxo", "i2s0", "i2s1";
0231 clocks = <&soc_clocks MMP2_CLK_AUDIO>,
0232 <&soc_clocks MMP2_CLK_VCTCXO>,
0233 <&soc_clocks MMP2_CLK_I2S0>,
0234 <&soc_clocks MMP2_CLK_I2S1>;
0235 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
0236 #clock-cells = <1>;
0237 status = "disabled";
0238 };
0239
0240 sspa0: audio-controller@d42a0c00 {
0241 compatible = "marvell,mmp-sspa";
0242 reg = <0xd42a0c00 0x30>,
0243 <0xd42a0c80 0x30>;
0244 interrupts = <2>;
0245 clock-names = "audio", "bitclk";
0246 clocks = <&soc_clocks MMP2_CLK_AUDIO>,
0247 <&audio_clk MMP2_CLK_AUDIO_SSPA0>;
0248 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
0249 #sound-dai-cells = <0>;
0250 status = "disabled";
0251 };
0252
0253 sspa1: audio-controller@d42a0d00 {
0254 compatible = "marvell,mmp-sspa";
0255 reg = <0xd42a0d00 0x30>,
0256 <0xd42a0d80 0x30>;
0257 interrupts = <3>;
0258 clock-names = "audio", "bitclk";
0259 clocks = <&soc_clocks MMP2_CLK_AUDIO>,
0260 <&audio_clk MMP2_CLK_AUDIO_SSPA1>;
0261 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
0262 #sound-dai-cells = <0>;
0263 status = "disabled";
0264 };
0265 };
0266
0267 apb@d4000000 { /* APB */
0268 compatible = "mrvl,apb-bus", "simple-bus";
0269 #address-cells = <1>;
0270 #size-cells = <1>;
0271 reg = <0xd4000000 0x00200000>;
0272 ranges;
0273
0274 dma-controller@d4000000 {
0275 compatible = "marvell,pdma-1.0";
0276 reg = <0xd4000000 0x10000>;
0277 interrupts = <48>;
0278 /* For backwards compatibility: */
0279 #dma-channels = <16>;
0280 dma-channels = <16>;
0281 status = "disabled";
0282 };
0283
0284 timer0: timer@d4014000 {
0285 compatible = "mrvl,mmp-timer";
0286 reg = <0xd4014000 0x100>;
0287 interrupts = <13>;
0288 clocks = <&soc_clocks MMP2_CLK_TIMER>;
0289 };
0290
0291 uart1: serial@d4030000 {
0292 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
0293 reg = <0xd4030000 0x1000>;
0294 interrupts = <27>;
0295 clocks = <&soc_clocks MMP2_CLK_UART0>;
0296 resets = <&soc_clocks MMP2_CLK_UART0>;
0297 reg-shift = <2>;
0298 status = "disabled";
0299 };
0300
0301 uart2: serial@d4017000 {
0302 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
0303 reg = <0xd4017000 0x1000>;
0304 interrupts = <28>;
0305 clocks = <&soc_clocks MMP2_CLK_UART1>;
0306 resets = <&soc_clocks MMP2_CLK_UART1>;
0307 reg-shift = <2>;
0308 status = "disabled";
0309 };
0310
0311 uart3: serial@d4018000 {
0312 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
0313 reg = <0xd4018000 0x1000>;
0314 interrupts = <24>;
0315 clocks = <&soc_clocks MMP2_CLK_UART2>;
0316 resets = <&soc_clocks MMP2_CLK_UART2>;
0317 reg-shift = <2>;
0318 status = "disabled";
0319 };
0320
0321 uart4: serial@d4016000 {
0322 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
0323 reg = <0xd4016000 0x1000>;
0324 interrupts = <46>;
0325 clocks = <&soc_clocks MMP2_CLK_UART3>;
0326 resets = <&soc_clocks MMP2_CLK_UART3>;
0327 reg-shift = <2>;
0328 status = "disabled";
0329 };
0330
0331 gpio: gpio@d4019000 {
0332 compatible = "marvell,mmp2-gpio";
0333 #address-cells = <1>;
0334 #size-cells = <1>;
0335 reg = <0xd4019000 0x1000>;
0336 gpio-controller;
0337 #gpio-cells = <2>;
0338 interrupts = <49>;
0339 interrupt-names = "gpio_mux";
0340 clocks = <&soc_clocks MMP2_CLK_GPIO>;
0341 resets = <&soc_clocks MMP2_CLK_GPIO>;
0342 interrupt-controller;
0343 #interrupt-cells = <2>;
0344 ranges;
0345
0346 gcb0: gpio@d4019000 {
0347 reg = <0xd4019000 0x4>;
0348 };
0349
0350 gcb1: gpio@d4019004 {
0351 reg = <0xd4019004 0x4>;
0352 };
0353
0354 gcb2: gpio@d4019008 {
0355 reg = <0xd4019008 0x4>;
0356 };
0357
0358 gcb3: gpio@d4019100 {
0359 reg = <0xd4019100 0x4>;
0360 };
0361
0362 gcb4: gpio@d4019104 {
0363 reg = <0xd4019104 0x4>;
0364 };
0365
0366 gcb5: gpio@d4019108 {
0367 reg = <0xd4019108 0x4>;
0368 };
0369 };
0370
0371 twsi1: i2c@d4011000 {
0372 compatible = "mrvl,mmp-twsi";
0373 reg = <0xd4011000 0x1000>;
0374 interrupts = <7>;
0375 clocks = <&soc_clocks MMP2_CLK_TWSI0>;
0376 resets = <&soc_clocks MMP2_CLK_TWSI0>;
0377 #address-cells = <1>;
0378 #size-cells = <0>;
0379 mrvl,i2c-fast-mode;
0380 status = "disabled";
0381 };
0382
0383 twsi2: i2c@d4031000 {
0384 compatible = "mrvl,mmp-twsi";
0385 reg = <0xd4031000 0x1000>;
0386 interrupt-parent = <&intcmux17>;
0387 interrupts = <0>;
0388 clocks = <&soc_clocks MMP2_CLK_TWSI1>;
0389 resets = <&soc_clocks MMP2_CLK_TWSI1>;
0390 #address-cells = <1>;
0391 #size-cells = <0>;
0392 status = "disabled";
0393 };
0394
0395 twsi3: i2c@d4032000 {
0396 compatible = "mrvl,mmp-twsi";
0397 reg = <0xd4032000 0x1000>;
0398 interrupt-parent = <&intcmux17>;
0399 interrupts = <1>;
0400 clocks = <&soc_clocks MMP2_CLK_TWSI2>;
0401 resets = <&soc_clocks MMP2_CLK_TWSI2>;
0402 #address-cells = <1>;
0403 #size-cells = <0>;
0404 status = "disabled";
0405 };
0406
0407 twsi4: i2c@d4033000 {
0408 compatible = "mrvl,mmp-twsi";
0409 reg = <0xd4033000 0x1000>;
0410 interrupt-parent = <&intcmux17>;
0411 interrupts = <2>;
0412 clocks = <&soc_clocks MMP2_CLK_TWSI3>;
0413 resets = <&soc_clocks MMP2_CLK_TWSI3>;
0414 #address-cells = <1>;
0415 #size-cells = <0>;
0416 status = "disabled";
0417 };
0418
0419
0420 twsi5: i2c@d4033800 {
0421 compatible = "mrvl,mmp-twsi";
0422 reg = <0xd4033800 0x1000>;
0423 interrupt-parent = <&intcmux17>;
0424 interrupts = <3>;
0425 clocks = <&soc_clocks MMP2_CLK_TWSI4>;
0426 resets = <&soc_clocks MMP2_CLK_TWSI4>;
0427 #address-cells = <1>;
0428 #size-cells = <0>;
0429 status = "disabled";
0430 };
0431
0432 twsi6: i2c@d4034000 {
0433 compatible = "mrvl,mmp-twsi";
0434 reg = <0xd4034000 0x1000>;
0435 interrupt-parent = <&intcmux17>;
0436 interrupts = <4>;
0437 clocks = <&soc_clocks MMP2_CLK_TWSI5>;
0438 resets = <&soc_clocks MMP2_CLK_TWSI5>;
0439 #address-cells = <1>;
0440 #size-cells = <0>;
0441 status = "disabled";
0442 };
0443
0444 rtc: rtc@d4010000 {
0445 compatible = "mrvl,mmp-rtc";
0446 reg = <0xd4010000 0x1000>;
0447 interrupts = <1>, <0>;
0448 interrupt-names = "rtc 1Hz", "rtc alarm";
0449 interrupt-parent = <&intcmux5>;
0450 clocks = <&soc_clocks MMP2_CLK_RTC>;
0451 resets = <&soc_clocks MMP2_CLK_RTC>;
0452 status = "disabled";
0453 };
0454
0455 ssp1: spi@d4035000 {
0456 compatible = "marvell,mmp2-ssp";
0457 reg = <0xd4035000 0x1000>;
0458 clocks = <&soc_clocks MMP2_CLK_SSP0>;
0459 interrupts = <0>;
0460 #address-cells = <1>;
0461 #size-cells = <0>;
0462 status = "disabled";
0463 };
0464
0465 ssp2: spi@d4036000 {
0466 compatible = "marvell,mmp2-ssp";
0467 reg = <0xd4036000 0x1000>;
0468 clocks = <&soc_clocks MMP2_CLK_SSP1>;
0469 interrupts = <1>;
0470 #address-cells = <1>;
0471 #size-cells = <0>;
0472 status = "disabled";
0473 };
0474
0475 ssp3: spi@d4037000 {
0476 compatible = "marvell,mmp2-ssp";
0477 reg = <0xd4037000 0x1000>;
0478 clocks = <&soc_clocks MMP2_CLK_SSP2>;
0479 interrupts = <20>;
0480 #address-cells = <1>;
0481 #size-cells = <0>;
0482 status = "disabled";
0483 };
0484
0485 ssp4: spi@d4039000 {
0486 compatible = "marvell,mmp2-ssp";
0487 reg = <0xd4039000 0x1000>;
0488 clocks = <&soc_clocks MMP2_CLK_SSP3>;
0489 interrupts = <21>;
0490 #address-cells = <1>;
0491 #size-cells = <0>;
0492 status = "disabled";
0493 };
0494 };
0495
0496 asram: sram@e0000000 {
0497 compatible = "mmio-sram";
0498 reg = <0xe0000000 0x10000>;
0499 ranges = <0 0xe0000000 0x10000>;
0500 #address-cells = <1>;
0501 #size-cells = <1>;
0502 status = "disabled";
0503 };
0504
0505 soc_clocks: clocks {
0506 compatible = "marvell,mmp2-clock";
0507 reg = <0xd4050000 0x2000>,
0508 <0xd4282800 0x400>,
0509 <0xd4015000 0x1000>;
0510 reg-names = "mpmu", "apmu", "apbc";
0511 #clock-cells = <1>;
0512 #reset-cells = <1>;
0513 #power-domain-cells = <1>;
0514 };
0515 };
0516 };
