0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <dt-bindings/interrupt-controller/irq.h>
0003 #include <dt-bindings/input/input.h>
0004 #include <dt-bindings/gpio/gpio.h>
0005 #include <dt-bindings/interrupt-controller/arm-gic.h>
0006
0007 / {
0008 compatible = "socionext,sc2000a";
0009 interrupt-parent = <&gic>;
0010 #address-cells = <1>;
0011 #size-cells = <1>;
0012
0013 cpus {
0014 #address-cells = <1>;
0015 #size-cells = <0>;
0016 enable-method = "socionext,milbeaut-m10v-smp";
0017 cpu@f00 {
0018 device_type = "cpu";
0019 compatible = "arm,cortex-a7";
0020 reg = <0xf00>;
0021 };
0022 cpu@f01 {
0023 device_type = "cpu";
0024 compatible = "arm,cortex-a7";
0025 reg = <0xf01>;
0026 };
0027 cpu@f02 {
0028 device_type = "cpu";
0029 compatible = "arm,cortex-a7";
0030 reg = <0xf02>;
0031 };
0032 cpu@f03 {
0033 device_type = "cpu";
0034 compatible = "arm,cortex-a7";
0035 reg = <0xf03>;
0036 };
0037 };
0038
0039 timer { /* The Generic Timer */
0040 compatible = "arm,armv7-timer";
0041 interrupts = <GIC_PPI 13
0042 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0043 <GIC_PPI 14
0044 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0045 <GIC_PPI 11
0046 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0047 <GIC_PPI 10
0048 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0049 clock-frequency = <40000000>;
0050 always-on;
0051 };
0052
0053 soc {
0054 compatible = "simple-bus";
0055 #address-cells = <1>;
0056 #size-cells = <1>;
0057 ranges;
0058 interrupt-parent = <&gic>;
0059
0060 gic: interrupt-controller@1d000000 {
0061 compatible = "arm,cortex-a7-gic";
0062 interrupt-controller;
0063 #interrupt-cells = <3>;
0064 reg = <0x1d001000 0x1000>,
0065 <0x1d002000 0x1000>; /* CPU I/f base and size */
0066 };
0067
0068 clk: clock-ctrl@1d021000 {
0069 compatible = "socionext,milbeaut-m10v-ccu";
0070 #clock-cells = <1>;
0071 reg = <0x1d021000 0x1000>;
0072 clocks = <&uclk40xi>;
0073 };
0074
0075 timer@1e000050 { /* 32-bit Reload Timers */
0076 compatible = "socionext,milbeaut-timer";
0077 reg = <0x1e000050 0x20>;
0078 interrupts = <0 91 4>;
0079 clocks = <&clk 4>;
0080 };
0081
0082 uart1: serial@1e700010 { /* PE4, PE5 */
0083 /* Enable this as ttyUSI0 */
0084 compatible = "socionext,milbeaut-usio-uart";
0085 reg = <0x1e700010 0x10>;
0086 interrupts = <0 141 0x4>, <0 149 0x4>;
0087 interrupt-names = "rx", "tx";
0088 clocks = <&clk 2>;
0089 };
0090
0091 };
0092
0093 sram@0 {
0094 compatible = "mmio-sram";
0095 reg = <0x0 0x10000>;
0096 #address-cells = <1>;
0097 #size-cells = <1>;
0098 ranges = <0 0x0 0x10000>;
0099 smp-sram@f100 {
0100 compatible = "socionext,milbeaut-smp-sram";
0101 reg = <0xf100 0x20>;
0102 };
0103 };
0104 };
