boot/dts/meson8m2.dtsi

0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003  * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
0004  */
0005
0006 #include "meson8.dtsi"
0007
0008 / {
0009         model = "Amlogic Meson8m2 SoC";
0010         compatible = "amlogic,meson8m2";
0011 }; /* end of / */
0012
0013 &clkc {
0014         compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
0015 };
0016
0017 &dmcbus {
0018         /* the offset of the canvas registers has changed compared to Meson8 */
0019         /delete-node/ video-lut@20;
0020
0021         canvas: video-lut@48 {
0022                 compatible = "amlogic,meson8m2-canvas", "amlogic,canvas";
0023                 reg = <0x48 0x14>;
0024         };
0025 };
0026
0027 &ethmac {
0028         compatible = "amlogic,meson8m2-dwmac", "snps,dwmac";
0029         reg = <0xc9410000 0x10000
0030                 0xc1108140 0x8>;
0031         clocks = <&clkc CLKID_ETH>,
0032                  <&clkc CLKID_MPLL2>,
0033                  <&clkc CLKID_MPLL2>,
0034                  <&clkc CLKID_FCLK_DIV2>;
0035         clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
0036         resets = <&reset RESET_ETHERNET>;
0037         reset-names = "stmmaceth";
0038 };
0039
0040 &pinctrl_aobus {
0041         compatible = "amlogic,meson8m2-aobus-pinctrl",
0042                      "amlogic,meson8-aobus-pinctrl";
0043 };
0044
0045 &pinctrl_cbus {
0046         compatible = "amlogic,meson8m2-cbus-pinctrl",
0047                      "amlogic,meson8-cbus-pinctrl";
0048
0049         eth_rgmii_pins: ethernet {
0050                 mux {
0051                         groups = "eth_tx_clk_50m", "eth_tx_en",
0052                                  "eth_txd3", "eth_txd2",
0053                                  "eth_txd1", "eth_txd0",
0054                                  "eth_rx_clk_in", "eth_rx_dv",
0055                                  "eth_rxd3", "eth_rxd2",
0056                                  "eth_rxd1", "eth_rxd0",
0057                                  "eth_mdio", "eth_mdc";
0058                         function = "ethernet";
0059                         bias-disable;
0060                 };
0061         };
0062 };
0063
0064 &pwrc {
0065         compatible = "amlogic,meson8m2-pwrc";
0066         resets = <&reset RESET_DBLK>,
0067                  <&reset RESET_PIC_DC>,
0068                  <&reset RESET_HDMI_APB>,
0069                  <&reset RESET_HDMI_SYSTEM_RESET>,
0070                  <&reset RESET_VENCI>,
0071                  <&reset RESET_VENCP>,
0072                  <&reset RESET_VDAC_4>,
0073                  <&reset RESET_VENCL>,
0074                  <&reset RESET_VIU>,
0075                  <&reset RESET_VENC>,
0076                  <&reset RESET_RDMA>;
0077         reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", "venci",
0078                       "vencp", "vdac", "vencl", "viu", "venc", "rdma";
0079         assigned-clocks = <&clkc CLKID_VPU>;
0080         assigned-clock-rates = <364000000>;
0081 };
0082
0083 &saradc {
0084         compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc";
0085 };
0086
0087 &sdhc {
0088         compatible = "amlogic,meson8m2-sdhc", "amlogic,meson-mx-sdhc";
0089 };
0090
0091 &usb0_phy {
0092         compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy";
0093 };
0094
0095 &usb1_phy {
0096         compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy";
0097 };
0098
0099 &wdt {
0100         compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt";
0101 };