0001 // SPDX-License-Identifier: GPL-2.0 OR MIT
0002 /*
0003 * Copyright 2014 Carlo Caione <carlo@caione.org>
0004 */
0005
0006 #include <dt-bindings/clock/meson8-ddr-clkc.h>
0007 #include <dt-bindings/clock/meson8b-clkc.h>
0008 #include <dt-bindings/gpio/meson8-gpio.h>
0009 #include <dt-bindings/power/meson8-power.h>
0010 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
0011 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
0012 #include <dt-bindings/thermal/thermal.h>
0013 #include "meson.dtsi"
0014
0015 / {
0016 model = "Amlogic Meson8 SoC";
0017 compatible = "amlogic,meson8";
0018
0019 cpus {
0020 #address-cells = <1>;
0021 #size-cells = <0>;
0022
0023 cpu0: cpu@200 {
0024 device_type = "cpu";
0025 compatible = "arm,cortex-a9";
0026 next-level-cache = <&L2>;
0027 reg = <0x200>;
0028 enable-method = "amlogic,meson8-smp";
0029 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
0030 operating-points-v2 = <&cpu_opp_table>;
0031 clocks = <&clkc CLKID_CPUCLK>;
0032 #cooling-cells = <2>; /* min followed by max */
0033 };
0034
0035 cpu1: cpu@201 {
0036 device_type = "cpu";
0037 compatible = "arm,cortex-a9";
0038 next-level-cache = <&L2>;
0039 reg = <0x201>;
0040 enable-method = "amlogic,meson8-smp";
0041 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
0042 operating-points-v2 = <&cpu_opp_table>;
0043 clocks = <&clkc CLKID_CPUCLK>;
0044 #cooling-cells = <2>; /* min followed by max */
0045 };
0046
0047 cpu2: cpu@202 {
0048 device_type = "cpu";
0049 compatible = "arm,cortex-a9";
0050 next-level-cache = <&L2>;
0051 reg = <0x202>;
0052 enable-method = "amlogic,meson8-smp";
0053 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
0054 operating-points-v2 = <&cpu_opp_table>;
0055 clocks = <&clkc CLKID_CPUCLK>;
0056 #cooling-cells = <2>; /* min followed by max */
0057 };
0058
0059 cpu3: cpu@203 {
0060 device_type = "cpu";
0061 compatible = "arm,cortex-a9";
0062 next-level-cache = <&L2>;
0063 reg = <0x203>;
0064 enable-method = "amlogic,meson8-smp";
0065 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
0066 operating-points-v2 = <&cpu_opp_table>;
0067 clocks = <&clkc CLKID_CPUCLK>;
0068 #cooling-cells = <2>; /* min followed by max */
0069 };
0070 };
0071
0072 cpu_opp_table: opp-table {
0073 compatible = "operating-points-v2";
0074 opp-shared;
0075
0076 opp-96000000 {
0077 opp-hz = /bits/ 64 <96000000>;
0078 opp-microvolt = <825000>;
0079 };
0080 opp-192000000 {
0081 opp-hz = /bits/ 64 <192000000>;
0082 opp-microvolt = <825000>;
0083 };
0084 opp-312000000 {
0085 opp-hz = /bits/ 64 <312000000>;
0086 opp-microvolt = <825000>;
0087 };
0088 opp-408000000 {
0089 opp-hz = /bits/ 64 <408000000>;
0090 opp-microvolt = <825000>;
0091 };
0092 opp-504000000 {
0093 opp-hz = /bits/ 64 <504000000>;
0094 opp-microvolt = <825000>;
0095 };
0096 opp-600000000 {
0097 opp-hz = /bits/ 64 <600000000>;
0098 opp-microvolt = <850000>;
0099 };
0100 opp-720000000 {
0101 opp-hz = /bits/ 64 <720000000>;
0102 opp-microvolt = <850000>;
0103 };
0104 opp-816000000 {
0105 opp-hz = /bits/ 64 <816000000>;
0106 opp-microvolt = <875000>;
0107 };
0108 opp-1008000000 {
0109 opp-hz = /bits/ 64 <1008000000>;
0110 opp-microvolt = <925000>;
0111 };
0112 opp-1200000000 {
0113 opp-hz = /bits/ 64 <1200000000>;
0114 opp-microvolt = <975000>;
0115 };
0116 opp-1416000000 {
0117 opp-hz = /bits/ 64 <1416000000>;
0118 opp-microvolt = <1025000>;
0119 };
0120 opp-1608000000 {
0121 opp-hz = /bits/ 64 <1608000000>;
0122 opp-microvolt = <1100000>;
0123 };
0124 opp-1800000000 {
0125 status = "disabled";
0126 opp-hz = /bits/ 64 <1800000000>;
0127 opp-microvolt = <1125000>;
0128 };
0129 opp-1992000000 {
0130 status = "disabled";
0131 opp-hz = /bits/ 64 <1992000000>;
0132 opp-microvolt = <1150000>;
0133 };
0134 };
0135
0136 gpu_opp_table: gpu-opp-table {
0137 compatible = "operating-points-v2";
0138
0139 opp-182142857 {
0140 opp-hz = /bits/ 64 <182142857>;
0141 opp-microvolt = <1150000>;
0142 };
0143 opp-318750000 {
0144 opp-hz = /bits/ 64 <318750000>;
0145 opp-microvolt = <1150000>;
0146 };
0147 opp-425000000 {
0148 opp-hz = /bits/ 64 <425000000>;
0149 opp-microvolt = <1150000>;
0150 };
0151 opp-510000000 {
0152 opp-hz = /bits/ 64 <510000000>;
0153 opp-microvolt = <1150000>;
0154 };
0155 opp-637500000 {
0156 opp-hz = /bits/ 64 <637500000>;
0157 opp-microvolt = <1150000>;
0158 turbo-mode;
0159 };
0160 };
0161
0162 pmu {
0163 compatible = "arm,cortex-a9-pmu";
0164 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
0165 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
0166 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
0167 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
0168 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0169 };
0170
0171 reserved-memory {
0172 #address-cells = <1>;
0173 #size-cells = <1>;
0174 ranges;
0175
0176 /* 2 MiB reserved for Hardware ROM Firmware? */
0177 hwrom@0 {
0178 reg = <0x0 0x200000>;
0179 no-map;
0180 };
0181
0182 /*
0183 * 1 MiB reserved for the "ARM Power Firmware": this is ARM
0184 * code which is responsible for system suspend. It loads a
0185 * piece of ARC code ("arc_power" in the vendor u-boot tree)
0186 * into SRAM, executes that and shuts down the (last) ARM core.
0187 * The arc_power firmware then checks various wakeup sources
0188 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
0189 * simply the power key) and re-starts the ARM core once it
0190 * detects a wakeup request.
0191 */
0192 power-firmware@4f00000 {
0193 reg = <0x4f00000 0x100000>;
0194 no-map;
0195 };
0196 };
0197
0198 thermal-zones {
0199 soc {
0200 polling-delay-passive = <250>; /* milliseconds */
0201 polling-delay = <1000>; /* milliseconds */
0202 thermal-sensors = <&thermal_sensor>;
0203
0204 cooling-maps {
0205 map0 {
0206 trip = <&soc_passive>;
0207 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0208 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0209 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0210 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0211 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0212 };
0213
0214 map1 {
0215 trip = <&soc_hot>;
0216 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0217 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0218 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0219 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0220 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0221 };
0222 };
0223
0224 trips {
0225 soc_passive: soc-passive {
0226 temperature = <80000>; /* millicelsius */
0227 hysteresis = <2000>; /* millicelsius */
0228 type = "passive";
0229 };
0230
0231 soc_hot: soc-hot {
0232 temperature = <90000>; /* millicelsius */
0233 hysteresis = <2000>; /* millicelsius */
0234 type = "hot";
0235 };
0236
0237 soc_critical: soc-critical {
0238 temperature = <110000>; /* millicelsius */
0239 hysteresis = <2000>; /* millicelsius */
0240 type = "critical";
0241 };
0242 };
0243 };
0244 };
0245
0246 mmcbus: bus@c8000000 {
0247 compatible = "simple-bus";
0248 reg = <0xc8000000 0x8000>;
0249 #address-cells = <1>;
0250 #size-cells = <1>;
0251 ranges = <0x0 0xc8000000 0x8000>;
0252
0253 ddr_clkc: clock-controller@400 {
0254 compatible = "amlogic,meson8-ddr-clkc";
0255 reg = <0x400 0x20>;
0256 clocks = <&xtal>;
0257 clock-names = "xtal";
0258 #clock-cells = <1>;
0259 };
0260
0261 dmcbus: bus@6000 {
0262 compatible = "simple-bus";
0263 reg = <0x6000 0x400>;
0264 #address-cells = <1>;
0265 #size-cells = <1>;
0266 ranges = <0x0 0x6000 0x400>;
0267
0268 canvas: video-lut@20 {
0269 compatible = "amlogic,meson8-canvas",
0270 "amlogic,canvas";
0271 reg = <0x20 0x14>;
0272 };
0273 };
0274 };
0275
0276 apb: bus@d0000000 {
0277 compatible = "simple-bus";
0278 reg = <0xd0000000 0x200000>;
0279 #address-cells = <1>;
0280 #size-cells = <1>;
0281 ranges = <0x0 0xd0000000 0x200000>;
0282
0283 mali: gpu@c0000 {
0284 compatible = "amlogic,meson8-mali", "arm,mali-450";
0285 reg = <0xc0000 0x40000>;
0286 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
0287 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
0288 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
0289 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
0290 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
0291 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
0292 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
0293 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
0294 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
0295 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
0296 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
0297 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
0298 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
0299 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
0300 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
0301 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
0302 interrupt-names = "gp", "gpmmu", "pp", "pmu",
0303 "pp0", "ppmmu0", "pp1", "ppmmu1",
0304 "pp2", "ppmmu2", "pp4", "ppmmu4",
0305 "pp5", "ppmmu5", "pp6", "ppmmu6";
0306 resets = <&reset RESET_MALI>;
0307
0308 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
0309 clock-names = "bus", "core";
0310
0311 assigned-clocks = <&clkc CLKID_MALI>;
0312 assigned-clock-rates = <318750000>;
0313
0314 operating-points-v2 = <&gpu_opp_table>;
0315 #cooling-cells = <2>; /* min followed by max */
0316 };
0317 };
0318 }; /* end of / */
0319
0320 &aiu {
0321 compatible = "amlogic,aiu-meson8", "amlogic,aiu";
0322 clocks = <&clkc CLKID_AIU_GLUE>,
0323 <&clkc CLKID_I2S_OUT>,
0324 <&clkc CLKID_AOCLK_GATE>,
0325 <&clkc CLKID_CTS_AMCLK>,
0326 <&clkc CLKID_MIXER_IFACE>,
0327 <&clkc CLKID_IEC958>,
0328 <&clkc CLKID_IEC958_GATE>,
0329 <&clkc CLKID_CTS_MCLK_I958>,
0330 <&clkc CLKID_CTS_I958>;
0331 clock-names = "pclk",
0332 "i2s_pclk",
0333 "i2s_aoclk",
0334 "i2s_mclk",
0335 "i2s_mixer",
0336 "spdif_pclk",
0337 "spdif_aoclk",
0338 "spdif_mclk",
0339 "spdif_mclk_sel";
0340 resets = <&reset RESET_AIU>;
0341 };
0342
0343 &aobus {
0344 pmu: pmu@e0 {
0345 compatible = "amlogic,meson8-pmu", "syscon";
0346 reg = <0xe0 0x18>;
0347 };
0348
0349 pinctrl_aobus: pinctrl@84 {
0350 compatible = "amlogic,meson8-aobus-pinctrl";
0351 reg = <0x84 0xc>;
0352 #address-cells = <1>;
0353 #size-cells = <1>;
0354 ranges;
0355
0356 gpio_ao: ao-bank@14 {
0357 reg = <0x14 0x4>,
0358 <0x2c 0x4>,
0359 <0x24 0x8>;
0360 reg-names = "mux", "pull", "gpio";
0361 gpio-controller;
0362 #gpio-cells = <2>;
0363 gpio-ranges = <&pinctrl_aobus 0 0 16>;
0364 };
0365
0366 i2s_am_clk_pins: i2s-am-clk-out {
0367 mux {
0368 groups = "i2s_am_clk_out_ao";
0369 function = "i2s_ao";
0370 bias-disable;
0371 };
0372 };
0373
0374 i2s_out_ao_clk_pins: i2s-ao-clk-out {
0375 mux {
0376 groups = "i2s_ao_clk_out_ao";
0377 function = "i2s_ao";
0378 bias-disable;
0379 };
0380 };
0381
0382 i2s_out_lr_clk_pins: i2s-lr-clk-out {
0383 mux {
0384 groups = "i2s_lr_clk_out_ao";
0385 function = "i2s_ao";
0386 bias-disable;
0387 };
0388 };
0389
0390 i2s_out_ch01_ao_pins: i2s-out-ch01 {
0391 mux {
0392 groups = "i2s_out_ch01_ao";
0393 function = "i2s_ao";
0394 bias-disable;
0395 };
0396 };
0397
0398 uart_ao_a_pins: uart_ao_a {
0399 mux {
0400 groups = "uart_tx_ao_a", "uart_rx_ao_a";
0401 function = "uart_ao";
0402 bias-disable;
0403 };
0404 };
0405
0406 i2c_ao_pins: i2c_mst_ao {
0407 mux {
0408 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
0409 function = "i2c_mst_ao";
0410 bias-disable;
0411 };
0412 };
0413
0414 ir_recv_pins: remote {
0415 mux {
0416 groups = "remote_input";
0417 function = "remote";
0418 bias-disable;
0419 };
0420 };
0421
0422 pwm_f_ao_pins: pwm-f-ao {
0423 mux {
0424 groups = "pwm_f_ao";
0425 function = "pwm_f_ao";
0426 bias-disable;
0427 };
0428 };
0429 };
0430 };
0431
0432 &ao_arc_rproc {
0433 compatible = "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc";
0434 amlogic,secbus2 = <&secbus2>;
0435 sram = <&ao_arc_sram>;
0436 resets = <&reset RESET_MEDIA_CPU>;
0437 clocks = <&clkc CLKID_AO_MEDIA_CPU>;
0438 };
0439
0440 &cbus {
0441 reset: reset-controller@4404 {
0442 compatible = "amlogic,meson8b-reset";
0443 reg = <0x4404 0x9c>;
0444 #reset-cells = <1>;
0445 };
0446
0447 analog_top: analog-top@81a8 {
0448 compatible = "amlogic,meson8-analog-top", "syscon";
0449 reg = <0x81a8 0x14>;
0450 };
0451
0452 pwm_ef: pwm@86c0 {
0453 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
0454 reg = <0x86c0 0x10>;
0455 #pwm-cells = <3>;
0456 status = "disabled";
0457 };
0458
0459 clock-measure@8758 {
0460 compatible = "amlogic,meson8-clk-measure";
0461 reg = <0x8758 0x1c>;
0462 };
0463
0464 pinctrl_cbus: pinctrl@9880 {
0465 compatible = "amlogic,meson8-cbus-pinctrl";
0466 reg = <0x9880 0x10>;
0467 #address-cells = <1>;
0468 #size-cells = <1>;
0469 ranges;
0470
0471 gpio: banks@80b0 {
0472 reg = <0x80b0 0x28>,
0473 <0x80e8 0x18>,
0474 <0x8120 0x18>,
0475 <0x8030 0x30>;
0476 reg-names = "mux", "pull", "pull-enable", "gpio";
0477 gpio-controller;
0478 #gpio-cells = <2>;
0479 gpio-ranges = <&pinctrl_cbus 0 0 120>;
0480 };
0481
0482 sd_a_pins: sd-a {
0483 mux {
0484 groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
0485 "sd_d3_a", "sd_clk_a", "sd_cmd_a";
0486 function = "sd_a";
0487 bias-disable;
0488 };
0489 };
0490
0491 sd_b_pins: sd-b {
0492 mux {
0493 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
0494 "sd_d3_b", "sd_clk_b", "sd_cmd_b";
0495 function = "sd_b";
0496 bias-disable;
0497 };
0498 };
0499
0500 sd_c_pins: sd-c {
0501 mux {
0502 groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
0503 "sd_d3_c", "sd_clk_c", "sd_cmd_c";
0504 function = "sd_c";
0505 bias-disable;
0506 };
0507 };
0508
0509 sdxc_b_pins: sdxc-b {
0510 mux {
0511 groups = "sdxc_d0_b", "sdxc_d13_b",
0512 "sdxc_clk_b", "sdxc_cmd_b";
0513 function = "sdxc_b";
0514 bias-pull-up;
0515 };
0516 };
0517
0518 spdif_out_pins: spdif-out {
0519 mux {
0520 groups = "spdif_out";
0521 function = "spdif";
0522 bias-disable;
0523 };
0524 };
0525
0526 spi_nor_pins: nor {
0527 mux {
0528 groups = "nor_d", "nor_q", "nor_c", "nor_cs";
0529 function = "nor";
0530 bias-disable;
0531 };
0532 };
0533
0534 eth_pins: ethernet {
0535 mux {
0536 groups = "eth_tx_clk_50m", "eth_tx_en",
0537 "eth_txd1", "eth_txd0",
0538 "eth_rx_clk_in", "eth_rx_dv",
0539 "eth_rxd1", "eth_rxd0", "eth_mdio",
0540 "eth_mdc";
0541 function = "ethernet";
0542 bias-disable;
0543 };
0544 };
0545
0546 pwm_e_pins: pwm-e {
0547 mux {
0548 groups = "pwm_e";
0549 function = "pwm_e";
0550 bias-disable;
0551 };
0552 };
0553
0554 uart_a1_pins: uart-a1 {
0555 mux {
0556 groups = "uart_tx_a1",
0557 "uart_rx_a1";
0558 function = "uart_a";
0559 bias-disable;
0560 };
0561 };
0562
0563 uart_a1_cts_rts_pins: uart-a1-cts-rts {
0564 mux {
0565 groups = "uart_cts_a1",
0566 "uart_rts_a1";
0567 function = "uart_a";
0568 bias-disable;
0569 };
0570 };
0571 };
0572 };
0573
0574 &ahb_sram {
0575 ao_arc_sram: ao-arc-sram@0 {
0576 compatible = "amlogic,meson8-ao-arc-sram";
0577 reg = <0x0 0x8000>;
0578 pool;
0579 };
0580
0581 smp-sram@1ff80 {
0582 compatible = "amlogic,meson8-smp-sram";
0583 reg = <0x1ff80 0x8>;
0584 };
0585 };
0586
0587 &efuse {
0588 compatible = "amlogic,meson8-efuse";
0589 clocks = <&clkc CLKID_EFUSE>;
0590 clock-names = "core";
0591
0592 temperature_calib: calib@1f4 {
0593 /* only the upper two bytes are relevant */
0594 reg = <0x1f4 0x4>;
0595 };
0596 };
0597
0598 ðmac {
0599 clocks = <&clkc CLKID_ETH>;
0600 clock-names = "stmmaceth";
0601
0602 power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
0603 };
0604
0605 &gpio_intc {
0606 compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc";
0607 status = "okay";
0608 };
0609
0610 &hhi {
0611 clkc: clock-controller {
0612 compatible = "amlogic,meson8-clkc";
0613 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
0614 clock-names = "xtal", "ddr_pll";
0615 #clock-cells = <1>;
0616 #reset-cells = <1>;
0617 };
0618
0619 pwrc: power-controller {
0620 compatible = "amlogic,meson8-pwrc";
0621 #power-domain-cells = <1>;
0622 amlogic,ao-sysctrl = <&pmu>;
0623 clocks = <&clkc CLKID_VPU>;
0624 clock-names = "vpu";
0625 assigned-clocks = <&clkc CLKID_VPU>;
0626 assigned-clock-rates = <364285714>;
0627 };
0628 };
0629
0630 &hwrng {
0631 compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
0632 clocks = <&clkc CLKID_RNG0>;
0633 clock-names = "core";
0634 };
0635
0636 &i2c_AO {
0637 clocks = <&clkc CLKID_CLK81>;
0638 };
0639
0640 &i2c_A {
0641 clocks = <&clkc CLKID_CLK81>;
0642 };
0643
0644 &i2c_B {
0645 clocks = <&clkc CLKID_CLK81>;
0646 };
0647
0648 &L2 {
0649 arm,data-latency = <3 3 3>;
0650 arm,tag-latency = <2 2 2>;
0651 arm,filter-ranges = <0x100000 0xc0000000>;
0652 prefetch-data = <1>;
0653 prefetch-instr = <1>;
0654 arm,shared-override;
0655 };
0656
0657 &periph {
0658 scu@0 {
0659 compatible = "arm,cortex-a9-scu";
0660 reg = <0x0 0x100>;
0661 };
0662
0663 timer@200 {
0664 compatible = "arm,cortex-a9-global-timer";
0665 reg = <0x200 0x20>;
0666 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
0667 clocks = <&clkc CLKID_PERIPH>;
0668
0669 /*
0670 * the arm_global_timer driver currently does not handle clock
0671 * rate changes. Keep it disabled for now.
0672 */
0673 status = "disabled";
0674 };
0675
0676 timer@600 {
0677 compatible = "arm,cortex-a9-twd-timer";
0678 reg = <0x600 0x20>;
0679 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
0680 clocks = <&clkc CLKID_PERIPH>;
0681 };
0682 };
0683
0684 &pwm_ab {
0685 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
0686 };
0687
0688 &pwm_cd {
0689 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
0690 };
0691
0692 &rtc {
0693 compatible = "amlogic,meson8-rtc";
0694 resets = <&reset RESET_RTC>;
0695 };
0696
0697 &saradc {
0698 compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
0699 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
0700 clock-names = "clkin", "core";
0701 amlogic,hhi-sysctrl = <&hhi>;
0702 nvmem-cells = <&temperature_calib>;
0703 nvmem-cell-names = "temperature_calib";
0704 };
0705
0706 &sdhc {
0707 compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
0708 clocks = <&xtal>,
0709 <&clkc CLKID_FCLK_DIV4>,
0710 <&clkc CLKID_FCLK_DIV3>,
0711 <&clkc CLKID_FCLK_DIV5>,
0712 <&clkc CLKID_SDHC>;
0713 clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
0714 };
0715
0716 &secbus {
0717 secbus2: system-controller@4000 {
0718 compatible = "amlogic,meson8-secbus2", "syscon";
0719 reg = <0x4000 0x2000>;
0720 };
0721 };
0722
0723 &sdio {
0724 compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
0725 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
0726 clock-names = "core", "clkin";
0727 };
0728
0729 &spifc {
0730 clocks = <&clkc CLKID_CLK81>;
0731 };
0732
0733 &timer_abcde {
0734 clocks = <&xtal>, <&clkc CLKID_CLK81>;
0735 clock-names = "xtal", "pclk";
0736 };
0737
0738 &uart_AO {
0739 compatible = "amlogic,meson8-uart", "amlogic,meson-ao-uart";
0740 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
0741 clock-names = "xtal", "pclk", "baud";
0742 };
0743
0744 &uart_A {
0745 compatible = "amlogic,meson8-uart";
0746 clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
0747 clock-names = "xtal", "pclk", "baud";
0748 };
0749
0750 &uart_B {
0751 compatible = "amlogic,meson8-uart";
0752 clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
0753 clock-names = "xtal", "pclk", "baud";
0754 };
0755
0756 &uart_C {
0757 compatible = "amlogic,meson8-uart";
0758 clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
0759 clock-names = "xtal", "pclk", "baud";
0760 };
0761
0762 &usb0 {
0763 compatible = "amlogic,meson8-usb", "snps,dwc2";
0764 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
0765 clock-names = "otg";
0766 };
0767
0768 &usb1 {
0769 compatible = "amlogic,meson8-usb", "snps,dwc2";
0770 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
0771 clock-names = "otg";
0772 };
0773
0774 &usb0_phy {
0775 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
0776 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
0777 clock-names = "usb_general", "usb";
0778 resets = <&reset RESET_USB_OTG>;
0779 };
0780
0781 &usb1_phy {
0782 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
0783 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
0784 clock-names = "usb_general", "usb";
0785 resets = <&reset RESET_USB_OTG>;
0786 };
