0001 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
0002 /*
0003 * Copyright 2018-2022 TQ-Systems GmbH
0004 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
0005 */
0006
0007 / {
0008 model = "TQ-Systems MBA6ULx Baseboard";
0009
0010 aliases {
0011 mmc0 = &usdhc2;
0012 mmc1 = &usdhc1;
0013 rtc0 = &rtc0;
0014 rtc1 = &snvs_rtc;
0015 };
0016
0017 chosen {
0018 stdout-path = &uart1;
0019 };
0020
0021 backlight: backlight {
0022 compatible = "pwm-backlight";
0023 power-supply = <®_mba6ul_3v3>;
0024 enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>;
0025 status = "disabled";
0026 };
0027
0028 beeper: beeper {
0029 compatible = "gpio-beeper";
0030 gpios = <&expander_out1 6 GPIO_ACTIVE_HIGH>;
0031 };
0032
0033 gpio_buttons: gpio-keys {
0034 compatible = "gpio-keys";
0035 pinctrl-names = "default";
0036 pinctrl-0 = <&pinctrl_buttons>;
0037
0038 button1 {
0039 label = "s14";
0040 linux,code = <KEY_1>;
0041 gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>;
0042 };
0043
0044 button2 {
0045 label = "s6";
0046 linux,code = <KEY_2>;
0047 gpios = <&expander_in0 1 GPIO_ACTIVE_LOW>;
0048 };
0049
0050 button3 {
0051 label = "s7";
0052 linux,code = <KEY_3>;
0053 gpios = <&expander_in0 2 GPIO_ACTIVE_LOW>;
0054 };
0055
0056 power-button {
0057 label = "POWER";
0058 linux,code = <KEY_POWER>;
0059 gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
0060 gpio-key,wakeup;
0061 };
0062 };
0063
0064 gpio-leds {
0065 compatible = "gpio-leds";
0066 status = "okay";
0067
0068 led1 {
0069 label = "led1";
0070 gpios = <&expander_out1 4 GPIO_ACTIVE_HIGH>;
0071 linux,default-trigger = "default-on";
0072 };
0073
0074 led2 {
0075 label = "led2";
0076 gpios = <&expander_out1 5 GPIO_ACTIVE_HIGH>;
0077 linux,default-trigger = "heartbeat";
0078 };
0079 };
0080
0081 reg_lcd_pwr: regulator-lcd-pwr {
0082 compatible = "regulator-fixed";
0083 regulator-name = "lcd-pwr";
0084 gpio = <&expander_out0 1 GPIO_ACTIVE_HIGH>;
0085 enable-active-high;
0086 status = "disabled";
0087 };
0088
0089 reg_mba6ul_3v3: regulator-mba6ul-3v3 {
0090 compatible = "regulator-fixed";
0091 regulator-name = "supply-mba6ul-3v3";
0092 regulator-min-microvolt = <3300000>;
0093 regulator-max-microvolt = <3300000>;
0094 regulator-always-on;
0095 };
0096
0097 reg_mba6ul_5v0: regulator-mba6ul-5v0 {
0098 compatible = "regulator-fixed";
0099 regulator-name = "supply-mba6ul-5v0";
0100 regulator-min-microvolt = <5000000>;
0101 regulator-max-microvolt = <5000000>;
0102 regulator-always-on;
0103 };
0104
0105 reg_mpcie: regulator-mpcie-3v3 {
0106 compatible = "regulator-fixed";
0107 regulator-name = "mpcie-3v3";
0108 regulator-min-microvolt = <3300000>;
0109 regulator-max-microvolt = <3300000>;
0110 gpio = <&expander_out0 2 GPIO_ACTIVE_HIGH>;
0111 enable-active-high;
0112 regulator-always-on;
0113 startup-delay-us = <500000>;
0114 vin-supply = <®_mba6ul_3v3>;
0115 };
0116
0117 reg_otg2vbus_5v0: regulator-otg2-vbus-5v0 {
0118 compatible = "regulator-fixed";
0119 gpio = <&expander_out1 0 GPIO_ACTIVE_HIGH>;
0120 enable-active-high;
0121 regulator-name = "otg2-vbus-supply-5v0";
0122 regulator-min-microvolt = <5000000>;
0123 regulator-max-microvolt = <5000000>;
0124 vin-supply = <®_mpcie>;
0125 };
0126
0127 reserved-memory {
0128 #address-cells = <1>;
0129 #size-cells = <1>;
0130 ranges;
0131
0132 linux,cma {
0133 compatible = "shared-dma-pool";
0134 reusable;
0135 size = <0x6000000>;
0136 linux,cma-default;
0137 };
0138 };
0139
0140 sound {
0141 compatible = "fsl,imx-audio-tlv320aic32x4";
0142 model = "imx-audio-tlv320aic32x4";
0143 ssi-controller = <&sai1>;
0144 audio-codec = <&tlv320aic32x4>;
0145 audio-asrc = <&asrc>;
0146 };
0147 };
0148
0149 &can1 {
0150 pinctrl-names = "default";
0151 pinctrl-0 = <&pinctrl_flexcan1>;
0152 xceiver-supply = <®_mba6ul_3v3>;
0153 status = "okay";
0154 };
0155
0156 &can2 {
0157 pinctrl-names = "default";
0158 pinctrl-0 = <&pinctrl_flexcan2>;
0159 xceiver-supply = <®_mba6ul_3v3>;
0160 status = "okay";
0161 };
0162
0163 &clks {
0164 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
0165 assigned-clock-rates = <768000000>;
0166 };
0167
0168 &ecspi2 {
0169 pinctrl-names = "default";
0170 pinctrl-0 = <&pinctrl_ecspi2>;
0171 num-cs = <1>;
0172 status = "okay";
0173 };
0174
0175 &fec1 {
0176 pinctrl-names = "default";
0177 pinctrl-0 = <&pinctrl_enet1>;
0178 phy-mode = "rmii";
0179 phy-handle = <ðphy0>;
0180 phy-supply = <®_mba6ul_3v3>;
0181 phy-reset-gpios = <&expander_out1 1 GPIO_ACTIVE_LOW>;
0182 phy-reset-duration = <25>;
0183 phy-reset-post-delay = <1>;
0184 status = "okay";
0185 };
0186
0187 &fec2 {
0188 pinctrl-names = "default";
0189 pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_mdc>;
0190 phy-mode = "rmii";
0191 phy-handle = <ðphy1>;
0192 phy-supply = <®_mba6ul_3v3>;
0193 phy-reset-gpios = <&expander_out1 2 GPIO_ACTIVE_LOW>;
0194 phy-reset-duration = <25>;
0195 phy-reset-post-delay = <1>;
0196 status = "okay";
0197
0198 mdio {
0199 #address-cells = <1>;
0200 #size-cells = <0>;
0201
0202 ethphy0: ethernet-phy@0 {
0203 compatible = "ethernet-phy-ieee802.3-c22";
0204 clocks = <&clks IMX6UL_CLK_ENET_REF>;
0205 reg = <0>;
0206 max-speed = <100>;
0207 };
0208
0209 ethphy1: ethernet-phy@1 {
0210 compatible = "ethernet-phy-ieee802.3-c22";
0211 clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
0212 reg = <1>;
0213 max-speed = <100>;
0214 };
0215 };
0216 };
0217
0218 &i2c4 {
0219 tlv320aic32x4: audio-codec@18 {
0220 compatible = "ti,tlv320aic32x4";
0221 reg = <0x18>;
0222 clocks = <&clks IMX6UL_CLK_SAI1>;
0223 clock-names = "mclk";
0224 ldoin-supply = <®_mba6ul_3v3>;
0225 iov-supply = <®_mba6ul_3v3>;
0226 };
0227
0228 jc42: temperature-sensor@19 {
0229 compatible = "nxp,se97", "jedec,jc-42.4-temp";
0230 reg = <0x19>;
0231 };
0232
0233 expander_out0: gpio-expander@20 {
0234 compatible = "nxp,pca9554";
0235 reg = <0x20>;
0236 gpio-controller;
0237 #gpio-cells = <2>;
0238 };
0239
0240 expander_in0: gpio-expander@21 {
0241 compatible = "nxp,pca9554";
0242 reg = <0x21>;
0243 pinctrl-names = "default";
0244 pinctrl-0 = <&pinctrl_expander_in0>;
0245 interrupt-parent = <&gpio4>;
0246 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
0247 interrupt-controller;
0248 #interrupt-cells = <2>;
0249 gpio-controller;
0250 #gpio-cells = <2>;
0251
0252 enet1_int-hog {
0253 gpio-hog;
0254 gpios = <6 0>;
0255 input;
0256 };
0257
0258 enet2_int-hog {
0259 gpio-hog;
0260 gpios = <7 0>;
0261 input;
0262 };
0263 };
0264
0265 expander_out1: gpio-expander@22 {
0266 compatible = "nxp,pca9554";
0267 reg = <0x22>;
0268 gpio-controller;
0269 #gpio-cells = <2>;
0270 };
0271
0272 analog_touch: touchscreen@41 {
0273 compatible = "st,stmpe811";
0274 reg = <0x41>;
0275 interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
0276 interrupt-parent = <&gpio4>;
0277 interrupt-controller;
0278 status = "disabled";
0279
0280 stmpe_touchscreen {
0281 compatible = "st,stmpe-ts";
0282 st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */
0283 st,ave-ctrl = <3>; /* 8 sample average control */
0284 st,fraction-z = <7>; /* 7 length fractional part in z */
0285 /*
0286 * 50 mA typical 80 mA max touchscreen drivers
0287 * current limit value
0288 */
0289 st,i-drive = <1>;
0290 st,mod-12b = <1>; /* 12-bit ADC */
0291 st,ref-sel = <0>; /* internal ADC reference */
0292 st,sample-time = <4>; /* ADC converstion time: 80 clocks */
0293 st,settling = <3>; /* 1 ms panel driver settling time */
0294 st,touch-det-delay = <5>; /* 5 ms touch detect interrupt delay */
0295 };
0296 };
0297
0298 /* NXP SE97BTP with temperature sensor + eeprom */
0299 se97b: eeprom@51 {
0300 compatible = "nxp,se97b", "atmel,24c02";
0301 reg = <0x51>;
0302 pagesize = <16>;
0303 };
0304 };
0305
0306 &pwm2 {
0307 pinctrl-names = "default";
0308 pinctrl-0 = <&pinctrl_pwm2>;
0309 status = "okay";
0310 };
0311
0312 &sai1 {
0313 pinctrl-names = "default";
0314 pinctrl-0 = <&pinctrl_sai1>;
0315 assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>,
0316 <&clks IMX6UL_CLK_SAI1>;
0317 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
0318 assigned-clock-rates = <0>, <24000000>;
0319 fsl,sai-mclk-direction-output;
0320 status = "okay";
0321 };
0322
0323 &uart1 {
0324 pinctrl-names = "default";
0325 pinctrl-0 = <&pinctrl_uart1>;
0326 status = "okay";
0327 };
0328
0329 &uart3 {
0330 pinctrl-names = "default";
0331 pinctrl-0 = <&pinctrl_uart3>;
0332 status = "okay";
0333 };
0334
0335 &uart6 {
0336 pinctrl-names = "default";
0337 pinctrl-0 = <&pinctrl_uart6>;
0338 /* for DTE mode, add below change */
0339 /* fsl,dte-mode; */
0340 /* pinctrl-0 = <&pinctrl_uart6dte>; */
0341 uart-has-rtscts;
0342 linux,rs485-enabled-at-boot-time;
0343 rs485-rts-active-low;
0344 rs485-rx-during-tx;
0345 status = "okay";
0346 };
0347
0348 /* otg-port */
0349 &usbotg1 {
0350 pinctrl-names = "default";
0351 pinctrl-0 = <&pinctrl_usb_otg1>;
0352 power-active-high;
0353 over-current-active-low;
0354 /* we implement only dual role but not a fully featured OTG */
0355 hnp-disable;
0356 srp-disable;
0357 adp-disable;
0358 dr_mode = "otg";
0359 status = "okay";
0360 };
0361
0362 /* 7-port usb hub */
0363 /* id, pwr, oc pins not connected */
0364 &usbotg2 {
0365 disable-over-current;
0366 vbus-supply = <®_otg2vbus_5v0>;
0367 dr_mode = "host";
0368 status = "okay";
0369 };
0370
0371 &usdhc1 {
0372 pinctrl-names = "default";
0373 pinctrl-0 = <&pinctrl_usdhc1>;
0374 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
0375 wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
0376 bus-width = <4>;
0377 vmmc-supply = <®_mba6ul_3v3>;
0378 vqmmc-supply = <®_vccsd>;
0379 no-1-8-v;
0380 no-mmc;
0381 no-sdio;
0382 status = "okay";
0383 };
0384
0385 &wdog1 {
0386 pinctrl-names = "default";
0387 pinctrl-0 = <&pinctrl_wdog1>;
0388 fsl,ext-reset-output;
0389 status = "okay";
0390 };
0391
0392 &iomuxc {
0393 pinctrl_buttons: buttonsgrp {
0394 fsl,pins = <
0395 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x100b0
0396 >;
0397 };
0398
0399 pinctrl_ecspi2: ecspi2grp {
0400 fsl,pins = <
0401 MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x1b020
0402 MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x1b020
0403 MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x1b020
0404 MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x1b020
0405 >;
0406 };
0407
0408 pinctrl_enet1: enet1grp {
0409 fsl,pins = <
0410 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
0411 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
0412 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
0413 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
0414 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
0415 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
0416 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
0417 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8
0418 >;
0419 };
0420
0421 pinctrl_enet2: enet2grp {
0422 fsl,pins = <
0423 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
0424 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
0425 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
0426 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
0427 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0
0428 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0
0429 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
0430 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8
0431 >;
0432 };
0433
0434 pinctrl_enet2_mdc: enet2mdcgrp {
0435 fsl,pins = <
0436 /* mdio */
0437 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
0438 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
0439 >;
0440 };
0441
0442 pinctrl_expander_in0: expanderin0grp {
0443 fsl,pins = <
0444 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1b0b1
0445 >;
0446 };
0447
0448 pinctrl_flexcan1: flexcan1grp {
0449 fsl,pins = <
0450 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
0451 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
0452 >;
0453 };
0454
0455 pinctrl_flexcan2: flexcan2grp {
0456 fsl,pins = <
0457 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
0458 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
0459 >;
0460 };
0461
0462 pinctrl_pwm2: pwm2grp {
0463 fsl,pins = <
0464 /* 100 k PD, DSE 120 OHM, SPPEED LO */
0465 MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x00003050
0466 >;
0467 };
0468
0469 pinctrl_sai1: sai1grp {
0470 fsl,pins = <
0471 MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b1
0472 MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b1
0473 MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8
0474 MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0
0475 MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b1
0476 >;
0477 };
0478
0479 pinctrl_uart1: uart1grp {
0480 fsl,pins = <
0481 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
0482 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
0483 >;
0484 };
0485
0486 pinctrl_uart3: uart3grp {
0487 fsl,pins = <
0488 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
0489 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
0490 >;
0491 };
0492
0493 pinctrl_uart6: uart6grp {
0494 fsl,pins = <
0495 MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
0496 MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
0497 MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1
0498 MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1
0499 >;
0500 };
0501
0502 pinctrl_uart6dte: uart6dte {
0503 fsl,pins = <
0504 MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x1b0b1
0505 MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x1b0b1
0506 MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x1b0b1
0507 MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x1b0b1
0508 >;
0509 };
0510
0511 pinctrl_usb_otg1: usbotg1grp {
0512 fsl,pins = <
0513 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x00017059
0514 MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0001b0b0
0515 MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x0001b099
0516 >;
0517 };
0518
0519 pinctrl_usdhc1: usdhc1grp {
0520 fsl,pins = <
0521 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069
0522 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017059
0523 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017059
0524 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017059
0525 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017059
0526 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017059
0527 /* WP */
0528 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099
0529 /* CD */
0530 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099
0531 >;
0532 };
0533
0534 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
0535 fsl,pins = <
0536 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069
0537 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170b9
0538 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170b9
0539 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170b9
0540 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170b9
0541 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170b9
0542 /* WP */
0543 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099
0544 /* CD */
0545 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099
0546 >;
0547 };
0548
0549 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
0550 fsl,pins = <
0551 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069
0552 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170f9
0553 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170f9
0554 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170f9
0555 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170f9
0556 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170f9
0557 /* WP */
0558 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099
0559 /* CD */
0560 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099
0561 >;
0562 };
0563
0564 pinctrl_wdog1: wdog1grp {
0565 fsl,pins = <
0566 MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0001b099
0567 >;
0568 };
0569 };
