0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2013-2014 Freescale Semiconductor, Inc.
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/thermal/thermal.h>
0008
0009 / {
0010 #address-cells = <2>;
0011 #size-cells = <2>;
0012 interrupt-parent = <&gic>;
0013
0014 aliases {
0015 crypto = &crypto;
0016 ethernet0 = &enet0;
0017 ethernet1 = &enet1;
0018 ethernet2 = &enet2;
0019 rtc1 = &ftm_alarm0;
0020 serial0 = &lpuart0;
0021 serial1 = &lpuart1;
0022 serial2 = &lpuart2;
0023 serial3 = &lpuart3;
0024 serial4 = &lpuart4;
0025 serial5 = &lpuart5;
0026 sysclk = &sysclk;
0027 };
0028
0029 cpus {
0030 #address-cells = <1>;
0031 #size-cells = <0>;
0032
0033 cpu0: cpu@f00 {
0034 compatible = "arm,cortex-a7";
0035 device_type = "cpu";
0036 reg = <0xf00>;
0037 clocks = <&clockgen 1 0>;
0038 #cooling-cells = <2>;
0039 };
0040
0041 cpu1: cpu@f01 {
0042 compatible = "arm,cortex-a7";
0043 device_type = "cpu";
0044 reg = <0xf01>;
0045 clocks = <&clockgen 1 0>;
0046 #cooling-cells = <2>;
0047 };
0048 };
0049
0050 memory@0 {
0051 device_type = "memory";
0052 reg = <0x0 0x0 0x0 0x0>;
0053 };
0054
0055 sysclk: sysclk {
0056 compatible = "fixed-clock";
0057 #clock-cells = <0>;
0058 clock-frequency = <100000000>;
0059 clock-output-names = "sysclk";
0060 };
0061
0062 timer {
0063 compatible = "arm,armv7-timer";
0064 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0065 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0066 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0067 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
0068 };
0069
0070 pmu {
0071 compatible = "arm,cortex-a7-pmu";
0072 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
0073 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
0074 interrupt-affinity = <&cpu0>, <&cpu1>;
0075 };
0076
0077 reboot {
0078 compatible = "syscon-reboot";
0079 regmap = <&dcfg>;
0080 offset = <0xb0>;
0081 mask = <0x02>;
0082 };
0083
0084 soc {
0085 compatible = "simple-bus";
0086 #address-cells = <2>;
0087 #size-cells = <2>;
0088 device_type = "soc";
0089 interrupt-parent = <&gic>;
0090 ranges;
0091
0092 ddr: memory-controller@1080000 {
0093 compatible = "fsl,qoriq-memory-controller";
0094 reg = <0x0 0x1080000 0x0 0x1000>;
0095 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
0096 big-endian;
0097 };
0098
0099 gic: interrupt-controller@1400000 {
0100 compatible = "arm,gic-400", "arm,cortex-a7-gic";
0101 #interrupt-cells = <3>;
0102 interrupt-controller;
0103 reg = <0x0 0x1401000 0x0 0x1000>,
0104 <0x0 0x1402000 0x0 0x2000>,
0105 <0x0 0x1404000 0x0 0x2000>,
0106 <0x0 0x1406000 0x0 0x2000>;
0107 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
0108
0109 };
0110
0111 msi1: msi-controller@1570e00 {
0112 compatible = "fsl,ls1021a-msi";
0113 reg = <0x0 0x1570e00 0x0 0x8>;
0114 msi-controller;
0115 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
0116 };
0117
0118 msi2: msi-controller@1570e08 {
0119 compatible = "fsl,ls1021a-msi";
0120 reg = <0x0 0x1570e08 0x0 0x8>;
0121 msi-controller;
0122 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
0123 };
0124
0125 ifc: memory-controller@1530000 {
0126 compatible = "fsl,ifc";
0127 reg = <0x0 0x1530000 0x0 0x10000>;
0128 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0129 status = "disabled";
0130 };
0131
0132 sfp: efuse@1e80000 {
0133 compatible = "fsl,ls1021a-sfp";
0134 reg = <0x0 0x1e80000 0x0 0x10000>;
0135 clocks = <&clockgen 4 3>;
0136 clock-names = "sfp";
0137 };
0138
0139 dcfg: dcfg@1ee0000 {
0140 compatible = "fsl,ls1021a-dcfg", "syscon";
0141 reg = <0x0 0x1ee0000 0x0 0x1000>;
0142 big-endian;
0143 };
0144
0145 qspi: spi@1550000 {
0146 compatible = "fsl,ls1021a-qspi";
0147 #address-cells = <1>;
0148 #size-cells = <0>;
0149 reg = <0x0 0x1550000 0x0 0x10000>,
0150 <0x0 0x40000000 0x0 0x20000000>;
0151 reg-names = "QuadSPI", "QuadSPI-memory";
0152 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
0153 clock-names = "qspi_en", "qspi";
0154 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
0155 status = "disabled";
0156 };
0157
0158 esdhc: esdhc@1560000 {
0159 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
0160 reg = <0x0 0x1560000 0x0 0x10000>;
0161 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0162 clock-frequency = <0>;
0163 voltage-ranges = <1800 1800 3300 3300>;
0164 sdhci,auto-cmd12;
0165 big-endian;
0166 bus-width = <4>;
0167 status = "disabled";
0168 };
0169
0170 sata: sata@3200000 {
0171 compatible = "fsl,ls1021a-ahci";
0172 reg = <0x0 0x3200000 0x0 0x10000>,
0173 <0x0 0x20220520 0x0 0x4>;
0174 reg-names = "ahci", "sata-ecc";
0175 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
0176 clocks = <&clockgen 4 1>;
0177 dma-coherent;
0178 status = "disabled";
0179 };
0180
0181 scfg: scfg@1570000 {
0182 compatible = "fsl,ls1021a-scfg", "syscon";
0183 reg = <0x0 0x1570000 0x0 0x10000>;
0184 big-endian;
0185 #address-cells = <1>;
0186 #size-cells = <1>;
0187 ranges = <0x0 0x0 0x1570000 0x10000>;
0188
0189 extirq: interrupt-controller@1ac {
0190 compatible = "fsl,ls1021a-extirq";
0191 #interrupt-cells = <2>;
0192 #address-cells = <0>;
0193 interrupt-controller;
0194 reg = <0x1ac 4>;
0195 interrupt-map =
0196 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
0197 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
0198 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
0199 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
0200 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
0201 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
0202 interrupt-map-mask = <0x7 0x0>;
0203 };
0204 };
0205
0206 crypto: crypto@1700000 {
0207 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
0208 fsl,sec-era = <7>;
0209 #address-cells = <1>;
0210 #size-cells = <1>;
0211 reg = <0x0 0x1700000 0x0 0x100000>;
0212 ranges = <0x0 0x0 0x1700000 0x100000>;
0213 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0214 dma-coherent;
0215
0216 sec_jr0: jr@10000 {
0217 compatible = "fsl,sec-v5.0-job-ring",
0218 "fsl,sec-v4.0-job-ring";
0219 reg = <0x10000 0x10000>;
0220 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0221 };
0222
0223 sec_jr1: jr@20000 {
0224 compatible = "fsl,sec-v5.0-job-ring",
0225 "fsl,sec-v4.0-job-ring";
0226 reg = <0x20000 0x10000>;
0227 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
0228 };
0229
0230 sec_jr2: jr@30000 {
0231 compatible = "fsl,sec-v5.0-job-ring",
0232 "fsl,sec-v4.0-job-ring";
0233 reg = <0x30000 0x10000>;
0234 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0235 };
0236
0237 sec_jr3: jr@40000 {
0238 compatible = "fsl,sec-v5.0-job-ring",
0239 "fsl,sec-v4.0-job-ring";
0240 reg = <0x40000 0x10000>;
0241 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0242 };
0243
0244 };
0245
0246 clockgen: clocking@1ee1000 {
0247 compatible = "fsl,ls1021a-clockgen";
0248 reg = <0x0 0x1ee1000 0x0 0x1000>;
0249 #clock-cells = <2>;
0250 clocks = <&sysclk>;
0251 };
0252
0253 tmu: tmu@1f00000 {
0254 compatible = "fsl,qoriq-tmu";
0255 reg = <0x0 0x1f00000 0x0 0x10000>;
0256 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0257 fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>;
0258 fsl,tmu-calibration = <0x00000000 0x00000020>,
0259 <0x00000001 0x00000024>,
0260 <0x00000002 0x0000002a>,
0261 <0x00000003 0x00000032>,
0262 <0x00000004 0x00000038>,
0263 <0x00000005 0x0000003e>,
0264 <0x00000006 0x00000043>,
0265 <0x00000007 0x0000004a>,
0266 <0x00000008 0x00000050>,
0267 <0x00000009 0x00000059>,
0268 <0x0000000a 0x0000005f>,
0269 <0x0000000b 0x00000066>,
0270
0271 <0x00010000 0x00000023>,
0272 <0x00010001 0x0000002b>,
0273 <0x00010002 0x00000033>,
0274 <0x00010003 0x0000003a>,
0275 <0x00010004 0x00000042>,
0276 <0x00010005 0x0000004a>,
0277 <0x00010006 0x00000054>,
0278 <0x00010007 0x0000005c>,
0279 <0x00010008 0x00000065>,
0280 <0x00010009 0x0000006f>,
0281
0282 <0x00020000 0x00000029>,
0283 <0x00020001 0x00000033>,
0284 <0x00020002 0x0000003d>,
0285 <0x00020003 0x00000048>,
0286 <0x00020004 0x00000054>,
0287 <0x00020005 0x00000060>,
0288 <0x00020006 0x0000006c>,
0289
0290 <0x00030000 0x00000025>,
0291 <0x00030001 0x00000033>,
0292 <0x00030002 0x00000043>,
0293 <0x00030003 0x00000055>;
0294 #thermal-sensor-cells = <1>;
0295 };
0296
0297 dspi0: spi@2100000 {
0298 compatible = "fsl,ls1021a-v1.0-dspi";
0299 #address-cells = <1>;
0300 #size-cells = <0>;
0301 reg = <0x0 0x2100000 0x0 0x10000>;
0302 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0303 clock-names = "dspi";
0304 clocks = <&clockgen 4 1>;
0305 spi-num-chipselects = <6>;
0306 big-endian;
0307 status = "disabled";
0308 };
0309
0310 dspi1: spi@2110000 {
0311 compatible = "fsl,ls1021a-v1.0-dspi";
0312 #address-cells = <1>;
0313 #size-cells = <0>;
0314 reg = <0x0 0x2110000 0x0 0x10000>;
0315 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0316 clock-names = "dspi";
0317 clocks = <&clockgen 4 1>;
0318 spi-num-chipselects = <6>;
0319 big-endian;
0320 status = "disabled";
0321 };
0322
0323 i2c0: i2c@2180000 {
0324 compatible = "fsl,vf610-i2c";
0325 #address-cells = <1>;
0326 #size-cells = <0>;
0327 reg = <0x0 0x2180000 0x0 0x10000>;
0328 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0329 clocks = <&clockgen 4 1>;
0330 dma-names = "rx", "tx";
0331 dmas = <&edma0 1 38>, <&edma0 1 39>;
0332 status = "disabled";
0333 };
0334
0335 i2c1: i2c@2190000 {
0336 compatible = "fsl,vf610-i2c";
0337 #address-cells = <1>;
0338 #size-cells = <0>;
0339 reg = <0x0 0x2190000 0x0 0x10000>;
0340 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0341 clocks = <&clockgen 4 1>;
0342 dma-names = "rx", "tx";
0343 dmas = <&edma0 1 36>, <&edma0 1 37>;
0344 status = "disabled";
0345 };
0346
0347 i2c2: i2c@21a0000 {
0348 compatible = "fsl,vf610-i2c";
0349 #address-cells = <1>;
0350 #size-cells = <0>;
0351 reg = <0x0 0x21a0000 0x0 0x10000>;
0352 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0353 clocks = <&clockgen 4 1>;
0354 dma-names = "rx", "tx";
0355 dmas = <&edma0 1 34>, <&edma0 1 35>;
0356 status = "disabled";
0357 };
0358
0359 uart0: serial@21c0500 {
0360 compatible = "fsl,16550-FIFO64", "ns16550a";
0361 reg = <0x0 0x21c0500 0x0 0x100>;
0362 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0363 clock-frequency = <0>;
0364 fifo-size = <15>;
0365 status = "disabled";
0366 };
0367
0368 uart1: serial@21c0600 {
0369 compatible = "fsl,16550-FIFO64", "ns16550a";
0370 reg = <0x0 0x21c0600 0x0 0x100>;
0371 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0372 clock-frequency = <0>;
0373 fifo-size = <15>;
0374 status = "disabled";
0375 };
0376
0377 uart2: serial@21d0500 {
0378 compatible = "fsl,16550-FIFO64", "ns16550a";
0379 reg = <0x0 0x21d0500 0x0 0x100>;
0380 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0381 clock-frequency = <0>;
0382 fifo-size = <15>;
0383 status = "disabled";
0384 };
0385
0386 uart3: serial@21d0600 {
0387 compatible = "fsl,16550-FIFO64", "ns16550a";
0388 reg = <0x0 0x21d0600 0x0 0x100>;
0389 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0390 clock-frequency = <0>;
0391 fifo-size = <15>;
0392 status = "disabled";
0393 };
0394
0395 counter0: counter@29d0000 {
0396 compatible = "fsl,ftm-quaddec";
0397 reg = <0x0 0x29d0000 0x0 0x10000>;
0398 big-endian;
0399 status = "disabled";
0400 };
0401
0402 counter1: counter@29e0000 {
0403 compatible = "fsl,ftm-quaddec";
0404 reg = <0x0 0x29e0000 0x0 0x10000>;
0405 big-endian;
0406 status = "disabled";
0407 };
0408
0409 counter2: counter@29f0000 {
0410 compatible = "fsl,ftm-quaddec";
0411 reg = <0x0 0x29f0000 0x0 0x10000>;
0412 big-endian;
0413 status = "disabled";
0414 };
0415
0416 counter3: counter@2a00000 {
0417 compatible = "fsl,ftm-quaddec";
0418 reg = <0x0 0x2a00000 0x0 0x10000>;
0419 big-endian;
0420 status = "disabled";
0421 };
0422
0423 gpio0: gpio@2300000 {
0424 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
0425 reg = <0x0 0x2300000 0x0 0x10000>;
0426 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0427 gpio-controller;
0428 #gpio-cells = <2>;
0429 interrupt-controller;
0430 #interrupt-cells = <2>;
0431 };
0432
0433 gpio1: gpio@2310000 {
0434 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
0435 reg = <0x0 0x2310000 0x0 0x10000>;
0436 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0437 gpio-controller;
0438 #gpio-cells = <2>;
0439 interrupt-controller;
0440 #interrupt-cells = <2>;
0441 };
0442
0443 gpio2: gpio@2320000 {
0444 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
0445 reg = <0x0 0x2320000 0x0 0x10000>;
0446 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0447 gpio-controller;
0448 #gpio-cells = <2>;
0449 interrupt-controller;
0450 #interrupt-cells = <2>;
0451 };
0452
0453 gpio3: gpio@2330000 {
0454 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
0455 reg = <0x0 0x2330000 0x0 0x10000>;
0456 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
0457 gpio-controller;
0458 #gpio-cells = <2>;
0459 interrupt-controller;
0460 #interrupt-cells = <2>;
0461 };
0462
0463 lpuart0: serial@2950000 {
0464 compatible = "fsl,ls1021a-lpuart";
0465 reg = <0x0 0x2950000 0x0 0x1000>;
0466 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0467 clocks = <&sysclk>;
0468 clock-names = "ipg";
0469 status = "disabled";
0470 };
0471
0472 lpuart1: serial@2960000 {
0473 compatible = "fsl,ls1021a-lpuart";
0474 reg = <0x0 0x2960000 0x0 0x1000>;
0475 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0476 clocks = <&clockgen 4 1>;
0477 clock-names = "ipg";
0478 status = "disabled";
0479 };
0480
0481 lpuart2: serial@2970000 {
0482 compatible = "fsl,ls1021a-lpuart";
0483 reg = <0x0 0x2970000 0x0 0x1000>;
0484 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0485 clocks = <&clockgen 4 1>;
0486 clock-names = "ipg";
0487 status = "disabled";
0488 };
0489
0490 lpuart3: serial@2980000 {
0491 compatible = "fsl,ls1021a-lpuart";
0492 reg = <0x0 0x2980000 0x0 0x1000>;
0493 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0494 clocks = <&clockgen 4 1>;
0495 clock-names = "ipg";
0496 status = "disabled";
0497 };
0498
0499 lpuart4: serial@2990000 {
0500 compatible = "fsl,ls1021a-lpuart";
0501 reg = <0x0 0x2990000 0x0 0x1000>;
0502 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0503 clocks = <&clockgen 4 1>;
0504 clock-names = "ipg";
0505 status = "disabled";
0506 };
0507
0508 lpuart5: serial@29a0000 {
0509 compatible = "fsl,ls1021a-lpuart";
0510 reg = <0x0 0x29a0000 0x0 0x1000>;
0511 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0512 clocks = <&clockgen 4 1>;
0513 clock-names = "ipg";
0514 status = "disabled";
0515 };
0516
0517 pwm0: pwm@29d0000 {
0518 compatible = "fsl,vf610-ftm-pwm";
0519 #pwm-cells = <3>;
0520 reg = <0x0 0x29d0000 0x0 0x10000>;
0521 clock-names = "ftm_sys", "ftm_ext",
0522 "ftm_fix", "ftm_cnt_clk_en";
0523 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
0524 <&clockgen 4 1>, <&clockgen 4 1>;
0525 big-endian;
0526 status = "disabled";
0527 };
0528
0529 pwm1: pwm@29e0000 {
0530 compatible = "fsl,vf610-ftm-pwm";
0531 #pwm-cells = <3>;
0532 reg = <0x0 0x29e0000 0x0 0x10000>;
0533 clock-names = "ftm_sys", "ftm_ext",
0534 "ftm_fix", "ftm_cnt_clk_en";
0535 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
0536 <&clockgen 4 1>, <&clockgen 4 1>;
0537 big-endian;
0538 status = "disabled";
0539 };
0540
0541 pwm2: pwm@29f0000 {
0542 compatible = "fsl,vf610-ftm-pwm";
0543 #pwm-cells = <3>;
0544 reg = <0x0 0x29f0000 0x0 0x10000>;
0545 clock-names = "ftm_sys", "ftm_ext",
0546 "ftm_fix", "ftm_cnt_clk_en";
0547 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
0548 <&clockgen 4 1>, <&clockgen 4 1>;
0549 big-endian;
0550 status = "disabled";
0551 };
0552
0553 pwm3: pwm@2a00000 {
0554 compatible = "fsl,vf610-ftm-pwm";
0555 #pwm-cells = <3>;
0556 reg = <0x0 0x2a00000 0x0 0x10000>;
0557 clock-names = "ftm_sys", "ftm_ext",
0558 "ftm_fix", "ftm_cnt_clk_en";
0559 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
0560 <&clockgen 4 1>, <&clockgen 4 1>;
0561 big-endian;
0562 status = "disabled";
0563 };
0564
0565 pwm4: pwm@2a10000 {
0566 compatible = "fsl,vf610-ftm-pwm";
0567 #pwm-cells = <3>;
0568 reg = <0x0 0x2a10000 0x0 0x10000>;
0569 clock-names = "ftm_sys", "ftm_ext",
0570 "ftm_fix", "ftm_cnt_clk_en";
0571 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
0572 <&clockgen 4 1>, <&clockgen 4 1>;
0573 big-endian;
0574 status = "disabled";
0575 };
0576
0577 pwm5: pwm@2a20000 {
0578 compatible = "fsl,vf610-ftm-pwm";
0579 #pwm-cells = <3>;
0580 reg = <0x0 0x2a20000 0x0 0x10000>;
0581 clock-names = "ftm_sys", "ftm_ext",
0582 "ftm_fix", "ftm_cnt_clk_en";
0583 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
0584 <&clockgen 4 1>, <&clockgen 4 1>;
0585 big-endian;
0586 status = "disabled";
0587 };
0588
0589 pwm6: pwm@2a30000 {
0590 compatible = "fsl,vf610-ftm-pwm";
0591 #pwm-cells = <3>;
0592 reg = <0x0 0x2a30000 0x0 0x10000>;
0593 clock-names = "ftm_sys", "ftm_ext",
0594 "ftm_fix", "ftm_cnt_clk_en";
0595 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
0596 <&clockgen 4 1>, <&clockgen 4 1>;
0597 big-endian;
0598 status = "disabled";
0599 };
0600
0601 pwm7: pwm@2a40000 {
0602 compatible = "fsl,vf610-ftm-pwm";
0603 #pwm-cells = <3>;
0604 reg = <0x0 0x2a40000 0x0 0x10000>;
0605 clock-names = "ftm_sys", "ftm_ext",
0606 "ftm_fix", "ftm_cnt_clk_en";
0607 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
0608 <&clockgen 4 1>, <&clockgen 4 1>;
0609 big-endian;
0610 status = "disabled";
0611 };
0612
0613 wdog0: watchdog@2ad0000 {
0614 compatible = "fsl,imx21-wdt";
0615 reg = <0x0 0x2ad0000 0x0 0x10000>;
0616 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
0617 clocks = <&clockgen 4 1>;
0618 clock-names = "wdog-en";
0619 big-endian;
0620 };
0621
0622 sai1: sai@2b50000 {
0623 #sound-dai-cells = <0>;
0624 compatible = "fsl,vf610-sai";
0625 reg = <0x0 0x2b50000 0x0 0x10000>;
0626 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
0627 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
0628 <&clockgen 4 1>, <&clockgen 4 1>;
0629 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0630 dma-names = "tx", "rx";
0631 dmas = <&edma0 1 47>,
0632 <&edma0 1 46>;
0633 status = "disabled";
0634 };
0635
0636 sai2: sai@2b60000 {
0637 #sound-dai-cells = <0>;
0638 compatible = "fsl,vf610-sai";
0639 reg = <0x0 0x2b60000 0x0 0x10000>;
0640 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
0641 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
0642 <&clockgen 4 1>, <&clockgen 4 1>;
0643 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0644 dma-names = "tx", "rx";
0645 dmas = <&edma0 1 45>,
0646 <&edma0 1 44>;
0647 status = "disabled";
0648 };
0649
0650 edma0: edma@2c00000 {
0651 #dma-cells = <2>;
0652 compatible = "fsl,vf610-edma";
0653 reg = <0x0 0x2c00000 0x0 0x10000>,
0654 <0x0 0x2c10000 0x0 0x10000>,
0655 <0x0 0x2c20000 0x0 0x10000>;
0656 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
0657 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
0658 interrupt-names = "edma-tx", "edma-err";
0659 dma-channels = <32>;
0660 big-endian;
0661 clock-names = "dmamux0", "dmamux1";
0662 clocks = <&clockgen 4 1>,
0663 <&clockgen 4 1>;
0664 };
0665
0666 dcu: dcu@2ce0000 {
0667 compatible = "fsl,ls1021a-dcu";
0668 reg = <0x0 0x2ce0000 0x0 0x10000>;
0669 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
0670 clocks = <&clockgen 4 0>,
0671 <&clockgen 4 0>;
0672 clock-names = "dcu", "pix";
0673 big-endian;
0674 status = "disabled";
0675 };
0676
0677 mdio0: mdio@2d24000 {
0678 compatible = "gianfar";
0679 device_type = "mdio";
0680 #address-cells = <1>;
0681 #size-cells = <0>;
0682 reg = <0x0 0x2d24000 0x0 0x4000>,
0683 <0x0 0x2d10030 0x0 0x4>;
0684 };
0685
0686 mdio1: mdio@2d64000 {
0687 compatible = "gianfar";
0688 device_type = "mdio";
0689 #address-cells = <1>;
0690 #size-cells = <0>;
0691 reg = <0x0 0x2d64000 0x0 0x4000>,
0692 <0x0 0x2d50030 0x0 0x4>;
0693 };
0694
0695 ptp_clock@2d10e00 {
0696 compatible = "fsl,etsec-ptp";
0697 reg = <0x0 0x2d10e00 0x0 0xb0>;
0698 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
0699 fsl,tclk-period = <5>;
0700 fsl,tmr-prsc = <2>;
0701 fsl,tmr-add = <0xaaaaaaab>;
0702 fsl,tmr-fiper1 = <999999995>;
0703 fsl,tmr-fiper2 = <999999995>;
0704 fsl,max-adj = <499999999>;
0705 fsl,extts-fifo;
0706 };
0707
0708 enet0: ethernet@2d10000 {
0709 compatible = "fsl,etsec2";
0710 device_type = "network";
0711 #address-cells = <2>;
0712 #size-cells = <2>;
0713 interrupt-parent = <&gic>;
0714 model = "eTSEC";
0715 fsl,magic-packet;
0716 ranges;
0717 dma-coherent;
0718
0719 queue-group@2d10000 {
0720 #address-cells = <2>;
0721 #size-cells = <2>;
0722 reg = <0x0 0x2d10000 0x0 0x1000>;
0723 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
0724 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
0725 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
0726 };
0727
0728 queue-group@2d14000 {
0729 #address-cells = <2>;
0730 #size-cells = <2>;
0731 reg = <0x0 0x2d14000 0x0 0x1000>;
0732 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
0733 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
0734 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
0735 };
0736 };
0737
0738 enet1: ethernet@2d50000 {
0739 compatible = "fsl,etsec2";
0740 device_type = "network";
0741 #address-cells = <2>;
0742 #size-cells = <2>;
0743 interrupt-parent = <&gic>;
0744 model = "eTSEC";
0745 ranges;
0746 dma-coherent;
0747
0748 queue-group@2d50000 {
0749 #address-cells = <2>;
0750 #size-cells = <2>;
0751 reg = <0x0 0x2d50000 0x0 0x1000>;
0752 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
0753 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
0754 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
0755 };
0756
0757 queue-group@2d54000 {
0758 #address-cells = <2>;
0759 #size-cells = <2>;
0760 reg = <0x0 0x2d54000 0x0 0x1000>;
0761 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
0762 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
0763 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
0764 };
0765 };
0766
0767 enet2: ethernet@2d90000 {
0768 compatible = "fsl,etsec2";
0769 device_type = "network";
0770 #address-cells = <2>;
0771 #size-cells = <2>;
0772 interrupt-parent = <&gic>;
0773 model = "eTSEC";
0774 ranges;
0775 dma-coherent;
0776
0777 queue-group@2d90000 {
0778 #address-cells = <2>;
0779 #size-cells = <2>;
0780 reg = <0x0 0x2d90000 0x0 0x1000>;
0781 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
0782 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
0783 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
0784 };
0785
0786 queue-group@2d94000 {
0787 #address-cells = <2>;
0788 #size-cells = <2>;
0789 reg = <0x0 0x2d94000 0x0 0x1000>;
0790 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
0791 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
0792 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
0793 };
0794 };
0795
0796 usb2: usb@8600000 {
0797 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
0798 reg = <0x0 0x8600000 0x0 0x1000>;
0799 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
0800 dr_mode = "host";
0801 phy_type = "ulpi";
0802 };
0803
0804 usb3: usb@3100000 {
0805 compatible = "snps,dwc3";
0806 reg = <0x0 0x3100000 0x0 0x10000>;
0807 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
0808 dr_mode = "host";
0809 snps,quirk-frame-length-adjustment = <0x20>;
0810 snps,dis_rxdet_inp3_quirk;
0811 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
0812 };
0813
0814 pcie@3400000 {
0815 compatible = "fsl,ls1021a-pcie";
0816 reg = <0x00 0x03400000 0x0 0x00010000>, /* controller registers */
0817 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
0818 reg-names = "regs", "config";
0819 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
0820 fsl,pcie-scfg = <&scfg 0>;
0821 #address-cells = <3>;
0822 #size-cells = <2>;
0823 device_type = "pci";
0824 num-viewport = <6>;
0825 bus-range = <0x0 0xff>;
0826 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000>, /* downstream I/O */
0827 <0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0828 msi-parent = <&msi1>, <&msi2>;
0829 #interrupt-cells = <1>;
0830 interrupt-map-mask = <0 0 0 7>;
0831 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
0832 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
0833 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
0834 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
0835 status = "disabled";
0836 };
0837
0838 pcie@3500000 {
0839 compatible = "fsl,ls1021a-pcie";
0840 reg = <0x00 0x03500000 0x0 0x00010000>, /* controller registers */
0841 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
0842 reg-names = "regs", "config";
0843 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
0844 fsl,pcie-scfg = <&scfg 1>;
0845 #address-cells = <3>;
0846 #size-cells = <2>;
0847 device_type = "pci";
0848 num-viewport = <6>;
0849 bus-range = <0x0 0xff>;
0850 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000>, /* downstream I/O */
0851 <0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0852 msi-parent = <&msi1>, <&msi2>;
0853 #interrupt-cells = <1>;
0854 interrupt-map-mask = <0 0 0 7>;
0855 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
0856 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
0857 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
0858 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
0859 status = "disabled";
0860 };
0861
0862 can0: can@2a70000 {
0863 compatible = "fsl,ls1021ar2-flexcan";
0864 reg = <0x0 0x2a70000 0x0 0x1000>;
0865 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
0866 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
0867 clock-names = "ipg", "per";
0868 big-endian;
0869 };
0870
0871 can1: can@2a80000 {
0872 compatible = "fsl,ls1021ar2-flexcan";
0873 reg = <0x0 0x2a80000 0x0 0x1000>;
0874 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
0875 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
0876 clock-names = "ipg", "per";
0877 big-endian;
0878 };
0879
0880 can2: can@2a90000 {
0881 compatible = "fsl,ls1021ar2-flexcan";
0882 reg = <0x0 0x2a90000 0x0 0x1000>;
0883 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
0884 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
0885 clock-names = "ipg", "per";
0886 big-endian;
0887 };
0888
0889 can3: can@2aa0000 {
0890 compatible = "fsl,ls1021ar2-flexcan";
0891 reg = <0x0 0x2aa0000 0x0 0x1000>;
0892 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
0893 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
0894 clock-names = "ipg", "per";
0895 big-endian;
0896 };
0897
0898 ocram1: sram@10000000 {
0899 compatible = "mmio-sram";
0900 reg = <0x0 0x10000000 0x0 0x10000>;
0901 #address-cells = <1>;
0902 #size-cells = <1>;
0903 ranges = <0x0 0x0 0x10000000 0x10000>;
0904 };
0905
0906 ocram2: sram@10010000 {
0907 compatible = "mmio-sram";
0908 reg = <0x0 0x10010000 0x0 0x10000>;
0909 #address-cells = <1>;
0910 #size-cells = <1>;
0911 ranges = <0x0 0x0 0x10010000 0x10000>;
0912 };
0913
0914 qdma: dma-controller@8390000 {
0915 compatible = "fsl,ls1021a-qdma";
0916 reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
0917 <0x0 0x8389000 0x0 0x1000>, /* Status regs */
0918 <0x0 0x838a000 0x0 0x2000>; /* Block regs */
0919 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
0920 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
0921 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0922 interrupt-names = "qdma-error",
0923 "qdma-queue0", "qdma-queue1";
0924 #dma-cells = <2>;
0925 dma-channels = <8>;
0926 block-number = <1>;
0927 block-offset = <0x1000>;
0928 fsl,dma-queues = <2>;
0929 status-sizes = <64>;
0930 queue-sizes = <64 64>;
0931 big-endian;
0932 };
0933
0934 rcpm: power-controller@1ee2140 {
0935 compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
0936 reg = <0x0 0x1ee2140 0x0 0x8>;
0937 #fsl,rcpm-wakeup-cells = <2>;
0938 #power-domain-cells = <0>;
0939 };
0940
0941 ftm_alarm0: timer0@29d0000 {
0942 compatible = "fsl,ls1021a-ftm-alarm";
0943 reg = <0x0 0x29d0000 0x0 0x10000>;
0944 reg-names = "ftm";
0945 fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>;
0946 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
0947 big-endian;
0948 };
0949 };
0950
0951 thermal-zones {
0952 cpu_thermal: cpu-thermal {
0953 polling-delay-passive = <1000>;
0954 polling-delay = <5000>;
0955
0956 thermal-sensors = <&tmu 0>;
0957
0958 trips {
0959 cpu_alert: cpu-alert {
0960 temperature = <85000>;
0961 hysteresis = <2000>;
0962 type = "passive";
0963 };
0964 cpu_crit: cpu-crit {
0965 temperature = <95000>;
0966 hysteresis = <2000>;
0967 type = "critical";
0968 };
0969 };
0970
0971 cooling-maps {
0972 map0 {
0973 trip = <&cpu_alert>;
0974 cooling-device =
0975 <&cpu0 THERMAL_NO_LIMIT
0976 THERMAL_NO_LIMIT>,
0977 <&cpu1 THERMAL_NO_LIMIT
0978 THERMAL_NO_LIMIT>;
0979 };
0980 };
0981 };
0982 };
0983 };
