0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright 2016-2018 NXP Semiconductors
0003 * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
0004 */
0005
0006 /dts-v1/;
0007 #include "ls1021a.dtsi"
0008
0009 / {
0010 model = "NXP LS1021A-TSN Board";
0011 compatible = "fsl,ls1021a-tsn", "fsl,ls1021a";
0012
0013 sys_mclk: clock-mclk {
0014 compatible = "fixed-clock";
0015 #clock-cells = <0>;
0016 clock-frequency = <24576000>;
0017 };
0018
0019 reg_vdda_codec: regulator-3V3 {
0020 compatible = "regulator-fixed";
0021 regulator-name = "3P3V";
0022 regulator-min-microvolt = <3300000>;
0023 regulator-max-microvolt = <3300000>;
0024 regulator-always-on;
0025 };
0026
0027 reg_vddio_codec: regulator-2V5 {
0028 compatible = "regulator-fixed";
0029 regulator-name = "2P5V";
0030 regulator-min-microvolt = <2500000>;
0031 regulator-max-microvolt = <2500000>;
0032 regulator-always-on;
0033 };
0034 };
0035
0036 &dspi0 {
0037 bus-num = <0>;
0038 status = "okay";
0039
0040 /* ADG704BRMZ 1:4 SPI mux/demux */
0041 sja1105: ethernet-switch@1 {
0042 reg = <0x1>;
0043 #address-cells = <1>;
0044 #size-cells = <0>;
0045 compatible = "nxp,sja1105t";
0046 /* 12 MHz */
0047 spi-max-frequency = <12000000>;
0048 /* Sample data on trailing clock edge */
0049 spi-cpha;
0050 /* SPI controller settings for SJA1105 timing requirements */
0051 fsl,spi-cs-sck-delay = <1000>;
0052 fsl,spi-sck-cs-delay = <1000>;
0053
0054 ports {
0055 #address-cells = <1>;
0056 #size-cells = <0>;
0057
0058 port@0 {
0059 /* ETH5 written on chassis */
0060 label = "swp5";
0061 phy-handle = <&rgmii_phy6>;
0062 phy-mode = "rgmii-id";
0063 reg = <0>;
0064 };
0065
0066 port@1 {
0067 /* ETH2 written on chassis */
0068 label = "swp2";
0069 phy-handle = <&rgmii_phy3>;
0070 phy-mode = "rgmii-id";
0071 reg = <1>;
0072 };
0073
0074 port@2 {
0075 /* ETH3 written on chassis */
0076 label = "swp3";
0077 phy-handle = <&rgmii_phy4>;
0078 phy-mode = "rgmii-id";
0079 reg = <2>;
0080 };
0081
0082 port@3 {
0083 /* ETH4 written on chassis */
0084 label = "swp4";
0085 phy-handle = <&rgmii_phy5>;
0086 phy-mode = "rgmii-id";
0087 reg = <3>;
0088 };
0089
0090 port@4 {
0091 /* Internal port connected to eth2 */
0092 ethernet = <&enet2>;
0093 phy-mode = "rgmii";
0094 rx-internal-delay-ps = <0>;
0095 tx-internal-delay-ps = <0>;
0096 reg = <4>;
0097
0098 fixed-link {
0099 speed = <1000>;
0100 full-duplex;
0101 };
0102 };
0103 };
0104 };
0105 };
0106
0107 &enet0 {
0108 tbi-handle = <&tbi0>;
0109 phy-handle = <&sgmii_phy2>;
0110 phy-mode = "sgmii";
0111 status = "okay";
0112 };
0113
0114 &enet1 {
0115 tbi-handle = <&tbi1>;
0116 phy-handle = <&sgmii_phy1>;
0117 phy-mode = "sgmii";
0118 status = "okay";
0119 };
0120
0121 /* RGMII delays added via PCB traces */
0122 &enet2 {
0123 phy-mode = "rgmii";
0124 status = "okay";
0125
0126 fixed-link {
0127 speed = <1000>;
0128 full-duplex;
0129 };
0130 };
0131
0132 &esdhc {
0133 status = "okay";
0134 };
0135
0136 &i2c0 {
0137 status = "okay";
0138
0139 /* 3 axis accelerometer */
0140 accelerometer@1e {
0141 compatible = "fsl,fxls8471";
0142 reg = <0x1e>;
0143 };
0144
0145 /* Audio codec (SAI2) */
0146 audio-codec@2a {
0147 compatible = "fsl,sgtl5000";
0148 VDDIO-supply = <®_vddio_codec>;
0149 VDDA-supply = <®_vdda_codec>;
0150 #sound-dai-cells = <0>;
0151 clocks = <&sys_mclk>;
0152 reg = <0x2a>;
0153 };
0154
0155 /* Current sensing circuit for 1V VDDCORE PMIC rail */
0156 current-sensor@44 {
0157 compatible = "ti,ina220";
0158 shunt-resistor = <1000>;
0159 reg = <0x44>;
0160 };
0161
0162 /* Current sensing circuit for 12V VCC rail */
0163 current-sensor@45 {
0164 compatible = "ti,ina220";
0165 shunt-resistor = <1000>;
0166 reg = <0x45>;
0167 };
0168
0169 /* Thermal monitor - case */
0170 temperature-sensor@48 {
0171 compatible = "national,lm75";
0172 reg = <0x48>;
0173 };
0174
0175 /* Thermal monitor - chip */
0176 temperature-sensor@4c {
0177 compatible = "ti,tmp451";
0178 reg = <0x4c>;
0179 };
0180
0181 eeprom@51 {
0182 compatible = "atmel,24c32";
0183 reg = <0x51>;
0184 };
0185
0186 /* Unsupported devices:
0187 * - FXAS21002C Gyroscope at 0x20
0188 * - TI ADS7924 4-channel ADC at 0x49
0189 */
0190 };
0191
0192 &ifc {
0193 status = "disabled";
0194 };
0195
0196 &lpuart0 {
0197 status = "okay";
0198 };
0199
0200 &lpuart3 {
0201 status = "okay";
0202 };
0203
0204 &mdio0 {
0205 /* AR8031 */
0206 sgmii_phy1: ethernet-phy@1 {
0207 reg = <0x1>;
0208 /* SGMII1_PHY_INT_B: connected to IRQ2, active low */
0209 interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
0210 };
0211
0212 /* AR8031 */
0213 sgmii_phy2: ethernet-phy@2 {
0214 reg = <0x2>;
0215 /* SGMII2_PHY_INT_B: connected to IRQ2, active low */
0216 interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
0217 };
0218
0219 /* BCM5464 quad PHY */
0220 rgmii_phy3: ethernet-phy@3 {
0221 reg = <0x3>;
0222 };
0223
0224 rgmii_phy4: ethernet-phy@4 {
0225 reg = <0x4>;
0226 };
0227
0228 rgmii_phy5: ethernet-phy@5 {
0229 reg = <0x5>;
0230 };
0231
0232 rgmii_phy6: ethernet-phy@6 {
0233 reg = <0x6>;
0234 };
0235
0236 /* SGMII PCS for enet0 */
0237 tbi0: tbi-phy@1f {
0238 reg = <0x1f>;
0239 device_type = "tbi-phy";
0240 };
0241 };
0242
0243 &mdio1 {
0244 /* SGMII PCS for enet1 */
0245 tbi1: tbi-phy@1f {
0246 reg = <0x1f>;
0247 device_type = "tbi-phy";
0248 };
0249 };
0250
0251 &qspi {
0252 status = "okay";
0253
0254 flash@0 {
0255 /* Rev. A uses 64MB flash, Rev. B & C use 32MB flash */
0256 compatible = "jedec,spi-nor";
0257 spi-max-frequency = <20000000>;
0258 #address-cells = <1>;
0259 #size-cells = <1>;
0260 reg = <0>;
0261
0262 partitions {
0263 compatible = "fixed-partitions";
0264 #address-cells = <1>;
0265 #size-cells = <1>;
0266
0267 partition@0 {
0268 label = "RCW";
0269 reg = <0x0 0x40000>;
0270 };
0271
0272 partition@40000 {
0273 label = "U-Boot";
0274 reg = <0x40000 0x300000>;
0275 };
0276
0277 partition@340000 {
0278 label = "U-Boot Env";
0279 reg = <0x340000 0x100000>;
0280 };
0281 };
0282 };
0283 };
0284
0285 &sai2 {
0286 status = "okay";
0287 };
0288
0289 &sata {
0290 status = "okay";
0291 };
0292
0293 &uart0 {
0294 status = "okay";
0295 };
