0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2013-2014 Freescale Semiconductor, Inc.
0004 * Copyright 2018 NXP
0005 */
0006
0007 /dts-v1/;
0008 #include "ls1021a.dtsi"
0009
0010 / {
0011 model = "LS1021A QDS Board";
0012 compatible = "fsl,ls1021a-qds", "fsl,ls1021a";
0013
0014 aliases {
0015 enet0_rgmii_phy = &rgmii_phy1;
0016 enet1_rgmii_phy = &rgmii_phy2;
0017 enet2_rgmii_phy = &rgmii_phy3;
0018 enet0_sgmii_phy = &sgmii_phy1c;
0019 enet1_sgmii_phy = &sgmii_phy1d;
0020 };
0021
0022 sys_mclk: clock-mclk {
0023 compatible = "fixed-clock";
0024 #clock-cells = <0>;
0025 clock-frequency = <24576000>;
0026 };
0027
0028 reg_3p3v: regulator {
0029 compatible = "regulator-fixed";
0030 regulator-name = "3P3V";
0031 regulator-min-microvolt = <3300000>;
0032 regulator-max-microvolt = <3300000>;
0033 regulator-always-on;
0034 };
0035
0036 sound {
0037 compatible = "simple-audio-card";
0038 simple-audio-card,format = "i2s";
0039 simple-audio-card,widgets =
0040 "Microphone", "Microphone Jack",
0041 "Headphone", "Headphone Jack",
0042 "Speaker", "Speaker Ext",
0043 "Line", "Line In Jack";
0044 simple-audio-card,routing =
0045 "MIC_IN", "Microphone Jack",
0046 "Microphone Jack", "Mic Bias",
0047 "LINE_IN", "Line In Jack",
0048 "Headphone Jack", "HP_OUT",
0049 "Speaker Ext", "LINE_OUT";
0050
0051 simple-audio-card,cpu {
0052 sound-dai = <&sai2>;
0053 frame-master;
0054 bitclock-master;
0055 };
0056
0057 simple-audio-card,codec {
0058 sound-dai = <&codec>;
0059 frame-master;
0060 bitclock-master;
0061 };
0062 };
0063 };
0064
0065 &dspi0 {
0066 bus-num = <0>;
0067 status = "okay";
0068
0069 dspiflash: at45db021d@0 {
0070 #address-cells = <1>;
0071 #size-cells = <1>;
0072 compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
0073 spi-max-frequency = <16000000>;
0074 spi-cpol;
0075 spi-cpha;
0076 reg = <0>;
0077 };
0078 };
0079
0080 &enet0 {
0081 tbi-handle = <&tbi0>;
0082 phy-handle = <&sgmii_phy1c>;
0083 phy-connection-type = "sgmii";
0084 status = "okay";
0085 };
0086
0087 &enet1 {
0088 tbi-handle = <&tbi0>;
0089 phy-handle = <&sgmii_phy1d>;
0090 phy-connection-type = "sgmii";
0091 status = "okay";
0092 };
0093
0094 &enet2 {
0095 phy-handle = <&rgmii_phy3>;
0096 phy-connection-type = "rgmii-id";
0097 status = "okay";
0098 };
0099
0100 &esdhc {
0101 status = "okay";
0102 };
0103
0104 &i2c0 {
0105 status = "okay";
0106
0107 pca9547: mux@77 {
0108 compatible = "nxp,pca9547";
0109 reg = <0x77>;
0110 #address-cells = <1>;
0111 #size-cells = <0>;
0112
0113 i2c@0 {
0114 #address-cells = <1>;
0115 #size-cells = <0>;
0116 reg = <0x0>;
0117
0118 ds3232: rtc@68 {
0119 compatible = "dallas,ds3232";
0120 reg = <0x68>;
0121 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
0122 };
0123 };
0124
0125 i2c@2 {
0126 #address-cells = <1>;
0127 #size-cells = <0>;
0128 reg = <0x2>;
0129
0130 ina220@40 {
0131 compatible = "ti,ina220";
0132 reg = <0x40>;
0133 shunt-resistor = <1000>;
0134 };
0135
0136 ina220@41 {
0137 compatible = "ti,ina220";
0138 reg = <0x41>;
0139 shunt-resistor = <1000>;
0140 };
0141 };
0142
0143 i2c@3 {
0144 #address-cells = <1>;
0145 #size-cells = <0>;
0146 reg = <0x3>;
0147
0148 eeprom@56 {
0149 compatible = "atmel,24c512";
0150 reg = <0x56>;
0151 };
0152
0153 eeprom@57 {
0154 compatible = "atmel,24c512";
0155 reg = <0x57>;
0156 };
0157
0158 adt7461a@4c {
0159 compatible = "adi,adt7461a";
0160 reg = <0x4c>;
0161 };
0162 };
0163
0164 i2c@4 {
0165 #address-cells = <1>;
0166 #size-cells = <0>;
0167 reg = <0x4>;
0168
0169 codec: sgtl5000@2a {
0170 #sound-dai-cells = <0>;
0171 compatible = "fsl,sgtl5000";
0172 reg = <0x2a>;
0173 VDDA-supply = <®_3p3v>;
0174 VDDIO-supply = <®_3p3v>;
0175 clocks = <&sys_mclk>;
0176 };
0177 };
0178 };
0179 };
0180
0181 &ifc {
0182 #address-cells = <2>;
0183 #size-cells = <1>;
0184 /* NOR, NAND Flashes and FPGA on board */
0185 ranges = <0x0 0x0 0x0 0x60000000 0x08000000>,
0186 <0x2 0x0 0x0 0x7e800000 0x00010000>,
0187 <0x3 0x0 0x0 0x7fb00000 0x00000100>;
0188 status = "okay";
0189
0190 nor@0,0 {
0191 #address-cells = <1>;
0192 #size-cells = <1>;
0193 compatible = "cfi-flash";
0194 reg = <0x0 0x0 0x8000000>;
0195 big-endian;
0196 bank-width = <2>;
0197 device-width = <1>;
0198 };
0199
0200 nand@2,0 {
0201 compatible = "fsl,ifc-nand";
0202 reg = <0x2 0x0 0x10000>;
0203 };
0204
0205 fpga: board-control@3,0 {
0206 #address-cells = <1>;
0207 #size-cells = <1>;
0208 compatible = "simple-mfd";
0209 reg = <0x3 0x0 0x0000100>;
0210 bank-width = <1>;
0211 device-width = <1>;
0212 ranges = <0 3 0 0x100>;
0213
0214 mdio-mux-emi1 {
0215 compatible = "mdio-mux-mmioreg";
0216 mdio-parent-bus = <&mdio0>;
0217 #address-cells = <1>;
0218 #size-cells = <0>;
0219 reg = <0x54 1>; /* BRDCFG4 */
0220 mux-mask = <0xe0>; /* EMI1[2:0] */
0221
0222 /* Onboard PHYs */
0223 ls1021amdio0: mdio@0 {
0224 reg = <0>;
0225 #address-cells = <1>;
0226 #size-cells = <0>;
0227 rgmii_phy1: ethernet-phy@1 {
0228 reg = <0x1>;
0229 };
0230 };
0231
0232 ls1021amdio1: mdio@20 {
0233 reg = <0x20>;
0234 #address-cells = <1>;
0235 #size-cells = <0>;
0236 rgmii_phy2: ethernet-phy@2 {
0237 reg = <0x2>;
0238 };
0239 };
0240
0241 ls1021amdio2: mdio@40 {
0242 reg = <0x40>;
0243 #address-cells = <1>;
0244 #size-cells = <0>;
0245 rgmii_phy3: ethernet-phy@3 {
0246 reg = <0x3>;
0247 };
0248 };
0249
0250 ls1021amdio3: mdio@60 {
0251 reg = <0x60>;
0252 #address-cells = <1>;
0253 #size-cells = <0>;
0254 sgmii_phy1c: ethernet-phy@1c {
0255 reg = <0x1c>;
0256 };
0257 };
0258
0259 ls1021amdio4: mdio@80 {
0260 reg = <0x80>;
0261 #address-cells = <1>;
0262 #size-cells = <0>;
0263 sgmii_phy1d: ethernet-phy@1d {
0264 reg = <0x1d>;
0265 };
0266 };
0267 };
0268 };
0269 };
0270
0271 &lpuart0 {
0272 status = "okay";
0273 };
0274
0275 &mdio0 {
0276 tbi0: tbi-phy@8 {
0277 reg = <0x8>;
0278 device_type = "tbi-phy";
0279 };
0280 };
0281
0282 &qspi {
0283 status = "okay";
0284
0285 flash@0 {
0286 compatible = "jedec,spi-nor";
0287 #address-cells = <1>;
0288 #size-cells = <1>;
0289 spi-max-frequency = <20000000>;
0290 reg = <0>;
0291 spi-rx-bus-width = <4>;
0292 spi-tx-bus-width = <4>;
0293 };
0294 };
0295
0296 &sai2 {
0297 status = "okay";
0298 };
0299
0300 &sata {
0301 status = "okay";
0302 };
0303
0304 &uart0 {
0305 status = "okay";
0306 };
0307
0308 &uart1 {
0309 status = "okay";
0310 };
0311
0312 &can0 {
0313 status = "okay";
0314 };
0315
0316 &can1 {
0317 status = "okay";
0318 };
0319
0320 &can2 {
0321 status = "disabled";
0322 };
0323
0324 &can3 {
0325 status = "disabled";
0326 };
