0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * NXP LPC32xx SoC
0004 *
0005 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
0006 * Copyright 2012 Roland Stigge <stigge@antcom.de>
0007 */
0008
0009 #include <dt-bindings/clock/lpc32xx-clock.h>
0010 #include <dt-bindings/interrupt-controller/irq.h>
0011
0012 / {
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015 compatible = "nxp,lpc3220";
0016 interrupt-parent = <&mic>;
0017
0018 cpus {
0019 #address-cells = <1>;
0020 #size-cells = <0>;
0021
0022 cpu@0 {
0023 compatible = "arm,arm926ej-s";
0024 device_type = "cpu";
0025 reg = <0x0>;
0026 };
0027 };
0028
0029 clocks {
0030 xtal_32k: xtal_32k {
0031 compatible = "fixed-clock";
0032 #clock-cells = <0>;
0033 clock-frequency = <32768>;
0034 clock-output-names = "xtal_32k";
0035 };
0036
0037 xtal: xtal {
0038 compatible = "fixed-clock";
0039 #clock-cells = <0>;
0040 clock-frequency = <13000000>;
0041 clock-output-names = "xtal";
0042 };
0043 };
0044
0045 ahb {
0046 #address-cells = <1>;
0047 #size-cells = <1>;
0048 compatible = "simple-bus";
0049 ranges = <0x00000000 0x00000000 0x10000000>,
0050 <0x20000000 0x20000000 0x30000000>,
0051 <0xe0000000 0xe0000000 0x04000000>;
0052
0053 iram: sram@8000000 {
0054 compatible = "mmio-sram";
0055 reg = <0x08000000 0x20000>;
0056
0057 #address-cells = <1>;
0058 #size-cells = <1>;
0059 ranges = <0x00000000 0x08000000 0x20000>;
0060 };
0061
0062 /*
0063 * Enable either SLC or MLC
0064 */
0065 slc: flash@20020000 {
0066 compatible = "nxp,lpc3220-slc";
0067 reg = <0x20020000 0x1000>;
0068 clocks = <&clk LPC32XX_CLK_SLC>;
0069 status = "disabled";
0070 };
0071
0072 mlc: flash@200a8000 {
0073 compatible = "nxp,lpc3220-mlc";
0074 reg = <0x200a8000 0x11000>;
0075 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
0076 clocks = <&clk LPC32XX_CLK_MLC>;
0077 status = "disabled";
0078 };
0079
0080 dma: dma@31000000 {
0081 compatible = "arm,pl080", "arm,primecell";
0082 reg = <0x31000000 0x1000>;
0083 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
0084 clocks = <&clk LPC32XX_CLK_DMA>;
0085 clock-names = "apb_pclk";
0086 };
0087
0088 usb {
0089 #address-cells = <1>;
0090 #size-cells = <1>;
0091 compatible = "simple-bus";
0092 ranges = <0x0 0x31020000 0x00001000>;
0093
0094 /*
0095 * Enable either ohci or usbd (gadget)!
0096 */
0097 ohci: ohci@0 {
0098 compatible = "nxp,ohci-nxp", "usb-ohci";
0099 reg = <0x0 0x300>;
0100 interrupt-parent = <&sic1>;
0101 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
0102 clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
0103 status = "disabled";
0104 };
0105
0106 usbd: usbd@0 {
0107 compatible = "nxp,lpc3220-udc";
0108 reg = <0x0 0x300>;
0109 interrupt-parent = <&sic1>;
0110 interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
0111 <30 IRQ_TYPE_LEVEL_HIGH>,
0112 <28 IRQ_TYPE_LEVEL_HIGH>,
0113 <26 IRQ_TYPE_LEVEL_LOW>;
0114 clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
0115 status = "disabled";
0116 };
0117
0118 i2cusb: i2c@300 {
0119 compatible = "nxp,pnx-i2c";
0120 reg = <0x300 0x100>;
0121 interrupt-parent = <&sic1>;
0122 interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
0123 clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
0124 #address-cells = <1>;
0125 #size-cells = <0>;
0126 };
0127
0128 usbclk: clock-controller@f00 {
0129 compatible = "nxp,lpc3220-usb-clk";
0130 reg = <0xf00 0x100>;
0131 #clock-cells = <1>;
0132 };
0133 };
0134
0135 clcd: clcd@31040000 {
0136 compatible = "arm,pl111", "arm,primecell";
0137 reg = <0x31040000 0x1000>;
0138 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
0139 clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>;
0140 clock-names = "clcdclk", "apb_pclk";
0141 status = "disabled";
0142 };
0143
0144 mac: ethernet@31060000 {
0145 compatible = "nxp,lpc-eth";
0146 reg = <0x31060000 0x1000>;
0147 interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
0148 clocks = <&clk LPC32XX_CLK_MAC>;
0149 status = "disabled";
0150 };
0151
0152 emc: memory-controller@31080000 {
0153 compatible = "arm,pl175", "arm,primecell";
0154 reg = <0x31080000 0x1000>;
0155 clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
0156 clock-names = "mpmcclk", "apb_pclk";
0157 #address-cells = <1>;
0158 #size-cells = <1>;
0159
0160 ranges = <0 0xe0000000 0x01000000>,
0161 <1 0xe1000000 0x01000000>,
0162 <2 0xe2000000 0x01000000>,
0163 <3 0xe3000000 0x01000000>;
0164 status = "disabled";
0165 };
0166
0167 apb {
0168 #address-cells = <1>;
0169 #size-cells = <1>;
0170 compatible = "simple-bus";
0171 ranges = <0x20000000 0x20000000 0x30000000>;
0172
0173 /*
0174 * ssp0 and spi1 are shared pins;
0175 * enable one in your board dts, as needed.
0176 */
0177 ssp0: spi@20084000 {
0178 compatible = "arm,pl022", "arm,primecell";
0179 reg = <0x20084000 0x1000>;
0180 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
0181 clocks = <&clk LPC32XX_CLK_SSP0>;
0182 clock-names = "apb_pclk";
0183 #address-cells = <1>;
0184 #size-cells = <0>;
0185 status = "disabled";
0186 };
0187
0188 spi1: spi@20088000 {
0189 compatible = "nxp,lpc3220-spi";
0190 reg = <0x20088000 0x1000>;
0191 clocks = <&clk LPC32XX_CLK_SPI1>;
0192 #address-cells = <1>;
0193 #size-cells = <0>;
0194 status = "disabled";
0195 };
0196
0197 /*
0198 * ssp1 and spi2 are shared pins;
0199 * enable one in your board dts, as needed.
0200 */
0201 ssp1: spi@2008c000 {
0202 compatible = "arm,pl022", "arm,primecell";
0203 reg = <0x2008c000 0x1000>;
0204 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
0205 clocks = <&clk LPC32XX_CLK_SSP1>;
0206 clock-names = "apb_pclk";
0207 #address-cells = <1>;
0208 #size-cells = <0>;
0209 status = "disabled";
0210 };
0211
0212 spi2: spi@20090000 {
0213 compatible = "nxp,lpc3220-spi";
0214 reg = <0x20090000 0x1000>;
0215 clocks = <&clk LPC32XX_CLK_SPI2>;
0216 #address-cells = <1>;
0217 #size-cells = <0>;
0218 status = "disabled";
0219 };
0220
0221 i2s0: i2s@20094000 {
0222 compatible = "nxp,lpc3220-i2s";
0223 reg = <0x20094000 0x1000>;
0224 status = "disabled";
0225 };
0226
0227 sd: sd@20098000 {
0228 compatible = "arm,pl18x", "arm,primecell";
0229 reg = <0x20098000 0x1000>;
0230 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
0231 <13 IRQ_TYPE_LEVEL_HIGH>;
0232 clocks = <&clk LPC32XX_CLK_SD>;
0233 clock-names = "apb_pclk";
0234 status = "disabled";
0235 };
0236
0237 i2s1: i2s@2009c000 {
0238 compatible = "nxp,lpc3220-i2s";
0239 reg = <0x2009c000 0x1000>;
0240 status = "disabled";
0241 };
0242
0243 /* UART5 first since it is the default console, ttyS0 */
0244 uart5: serial@40090000 {
0245 /* actually, ns16550a w/ 64 byte fifos! */
0246 compatible = "nxp,lpc3220-uart";
0247 reg = <0x40090000 0x1000>;
0248 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
0249 reg-shift = <2>;
0250 clocks = <&clk LPC32XX_CLK_UART5>;
0251 status = "disabled";
0252 };
0253
0254 uart3: serial@40080000 {
0255 compatible = "nxp,lpc3220-uart";
0256 reg = <0x40080000 0x1000>;
0257 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
0258 reg-shift = <2>;
0259 clocks = <&clk LPC32XX_CLK_UART3>;
0260 status = "disabled";
0261 };
0262
0263 uart4: serial@40088000 {
0264 compatible = "nxp,lpc3220-uart";
0265 reg = <0x40088000 0x1000>;
0266 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
0267 reg-shift = <2>;
0268 clocks = <&clk LPC32XX_CLK_UART4>;
0269 status = "disabled";
0270 };
0271
0272 uart6: serial@40098000 {
0273 compatible = "nxp,lpc3220-uart";
0274 reg = <0x40098000 0x1000>;
0275 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
0276 reg-shift = <2>;
0277 clocks = <&clk LPC32XX_CLK_UART6>;
0278 status = "disabled";
0279 };
0280
0281 i2c1: i2c@400a0000 {
0282 compatible = "nxp,pnx-i2c";
0283 reg = <0x400a0000 0x100>;
0284 interrupt-parent = <&sic1>;
0285 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
0286 #address-cells = <1>;
0287 #size-cells = <0>;
0288 clocks = <&clk LPC32XX_CLK_I2C1>;
0289 };
0290
0291 i2c2: i2c@400a8000 {
0292 compatible = "nxp,pnx-i2c";
0293 reg = <0x400a8000 0x100>;
0294 interrupt-parent = <&sic1>;
0295 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
0296 #address-cells = <1>;
0297 #size-cells = <0>;
0298 clocks = <&clk LPC32XX_CLK_I2C2>;
0299 };
0300
0301 mpwm: mpwm@400e8000 {
0302 compatible = "nxp,lpc3220-motor-pwm";
0303 reg = <0x400e8000 0x78>;
0304 status = "disabled";
0305 #pwm-cells = <2>;
0306 };
0307 };
0308
0309 fab {
0310 #address-cells = <1>;
0311 #size-cells = <1>;
0312 compatible = "simple-bus";
0313 ranges = <0x20000000 0x20000000 0x30000000>;
0314
0315 /* System Control Block */
0316 scb {
0317 compatible = "simple-bus";
0318 ranges = <0x0 0x040004000 0x00001000>;
0319 #address-cells = <1>;
0320 #size-cells = <1>;
0321
0322 clk: clock-controller@0 {
0323 compatible = "nxp,lpc3220-clk";
0324 reg = <0x00 0x114>;
0325 #clock-cells = <1>;
0326
0327 clocks = <&xtal_32k>, <&xtal>;
0328 clock-names = "xtal_32k", "xtal";
0329 };
0330 };
0331
0332 mic: interrupt-controller@40008000 {
0333 compatible = "nxp,lpc3220-mic";
0334 reg = <0x40008000 0x4000>;
0335 interrupt-controller;
0336 #interrupt-cells = <2>;
0337 };
0338
0339 sic1: interrupt-controller@4000c000 {
0340 compatible = "nxp,lpc3220-sic";
0341 reg = <0x4000c000 0x4000>;
0342 interrupt-controller;
0343 #interrupt-cells = <2>;
0344
0345 interrupt-parent = <&mic>;
0346 interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
0347 <30 IRQ_TYPE_LEVEL_LOW>;
0348 };
0349
0350 sic2: interrupt-controller@40010000 {
0351 compatible = "nxp,lpc3220-sic";
0352 reg = <0x40010000 0x4000>;
0353 interrupt-controller;
0354 #interrupt-cells = <2>;
0355
0356 interrupt-parent = <&mic>;
0357 interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
0358 <31 IRQ_TYPE_LEVEL_LOW>;
0359 };
0360
0361 uart1: serial@40014000 {
0362 compatible = "nxp,lpc3220-hsuart";
0363 reg = <0x40014000 0x1000>;
0364 interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
0365 status = "disabled";
0366 };
0367
0368 uart2: serial@40018000 {
0369 compatible = "nxp,lpc3220-hsuart";
0370 reg = <0x40018000 0x1000>;
0371 interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
0372 status = "disabled";
0373 };
0374
0375 uart7: serial@4001c000 {
0376 compatible = "nxp,lpc3220-hsuart";
0377 reg = <0x4001c000 0x1000>;
0378 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
0379 status = "disabled";
0380 };
0381
0382 rtc: rtc@40024000 {
0383 compatible = "nxp,lpc3220-rtc";
0384 reg = <0x40024000 0x1000>;
0385 interrupt-parent = <&sic1>;
0386 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
0387 clocks = <&clk LPC32XX_CLK_RTC>;
0388 };
0389
0390 gpio: gpio@40028000 {
0391 compatible = "nxp,lpc3220-gpio";
0392 reg = <0x40028000 0x1000>;
0393 gpio-controller;
0394 #gpio-cells = <3>; /* bank, pin, flags */
0395 };
0396
0397 timer4: timer@4002c000 {
0398 compatible = "nxp,lpc3220-timer";
0399 reg = <0x4002c000 0x1000>;
0400 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
0401 clocks = <&clk LPC32XX_CLK_TIMER4>;
0402 clock-names = "timerclk";
0403 status = "disabled";
0404 };
0405
0406 timer5: timer@40030000 {
0407 compatible = "nxp,lpc3220-timer";
0408 reg = <0x40030000 0x1000>;
0409 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
0410 clocks = <&clk LPC32XX_CLK_TIMER5>;
0411 clock-names = "timerclk";
0412 status = "disabled";
0413 };
0414
0415 watchdog: watchdog@4003c000 {
0416 compatible = "nxp,pnx4008-wdt";
0417 reg = <0x4003c000 0x1000>;
0418 clocks = <&clk LPC32XX_CLK_WDOG>;
0419 };
0420
0421 timer0: timer@40044000 {
0422 compatible = "nxp,lpc3220-timer";
0423 reg = <0x40044000 0x1000>;
0424 clocks = <&clk LPC32XX_CLK_TIMER0>;
0425 clock-names = "timerclk";
0426 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
0427 };
0428
0429 /*
0430 * TSC vs. ADC: Since those two share the same
0431 * hardware, you need to choose from one of the
0432 * following two and do 'status = "okay";' for one of
0433 * them
0434 */
0435
0436 adc: adc@40048000 {
0437 compatible = "nxp,lpc3220-adc";
0438 reg = <0x40048000 0x1000>;
0439 interrupt-parent = <&sic1>;
0440 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
0441 clocks = <&clk LPC32XX_CLK_ADC>;
0442 status = "disabled";
0443 };
0444
0445 tsc: tsc@40048000 {
0446 compatible = "nxp,lpc3220-tsc";
0447 reg = <0x40048000 0x1000>;
0448 interrupt-parent = <&sic1>;
0449 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
0450 clocks = <&clk LPC32XX_CLK_ADC>;
0451 status = "disabled";
0452 };
0453
0454 timer1: timer@4004c000 {
0455 compatible = "nxp,lpc3220-timer";
0456 reg = <0x4004c000 0x1000>;
0457 interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
0458 clocks = <&clk LPC32XX_CLK_TIMER1>;
0459 clock-names = "timerclk";
0460 };
0461
0462 key: key@40050000 {
0463 compatible = "nxp,lpc3220-key";
0464 reg = <0x40050000 0x1000>;
0465 clocks = <&clk LPC32XX_CLK_KEY>;
0466 interrupt-parent = <&sic1>;
0467 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
0468 status = "disabled";
0469 };
0470
0471 timer2: timer@40058000 {
0472 compatible = "nxp,lpc3220-timer";
0473 reg = <0x40058000 0x1000>;
0474 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
0475 clocks = <&clk LPC32XX_CLK_TIMER2>;
0476 clock-names = "timerclk";
0477 status = "disabled";
0478 };
0479
0480 pwm1: pwm@4005c000 {
0481 compatible = "nxp,lpc3220-pwm";
0482 reg = <0x4005c000 0x4>;
0483 clocks = <&clk LPC32XX_CLK_PWM1>;
0484 assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
0485 assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
0486 status = "disabled";
0487 };
0488
0489 pwm2: pwm@4005c004 {
0490 compatible = "nxp,lpc3220-pwm";
0491 reg = <0x4005c004 0x4>;
0492 clocks = <&clk LPC32XX_CLK_PWM2>;
0493 assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
0494 assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
0495 status = "disabled";
0496 };
0497
0498 timer3: timer@40060000 {
0499 compatible = "nxp,lpc3220-timer";
0500 reg = <0x40060000 0x1000>;
0501 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
0502 clocks = <&clk LPC32XX_CLK_TIMER3>;
0503 clock-names = "timerclk";
0504 status = "disabled";
0505 };
0506 };
0507 };
0508 };
