0001 /*
0002 * Common base for NXP LPC18xx and LPC43xx devices.
0003 *
0004 * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
0005 *
0006 * This code is released using a dual license strategy: BSD/GPL
0007 * You can choose the licence that better fits your requirements.
0008 *
0009 * Released under the terms of 3-clause BSD License
0010 * Released under the terms of GNU General Public License Version 2.0
0011 *
0012 */
0013
0014 #include "armv7-m.dtsi"
0015
0016 #include "dt-bindings/clock/lpc18xx-cgu.h"
0017 #include "dt-bindings/clock/lpc18xx-ccu.h"
0018
0019 #define LPC_PIN(port, pin) (0x##port * 32 + pin)
0020 #define LPC_GPIO(port, pin) (port * 32 + pin)
0021
0022 / {
0023 #address-cells = <1>;
0024 #size-cells = <1>;
0025
0026 cpus {
0027 #address-cells = <1>;
0028 #size-cells = <0>;
0029
0030 cpu@0 {
0031 compatible = "arm,cortex-m3";
0032 device_type = "cpu";
0033 reg = <0x0>;
0034 clocks = <&ccu1 CLK_CPU_CORE>;
0035 };
0036 };
0037
0038 clocks {
0039 xtal: xtal {
0040 compatible = "fixed-clock";
0041 #clock-cells = <0>;
0042 clock-frequency = <12000000>;
0043 };
0044
0045 xtal32: xtal32 {
0046 compatible = "fixed-clock";
0047 #clock-cells = <0>;
0048 clock-frequency = <32768>;
0049 };
0050
0051 enet_rx_clk: enet_rx_clk {
0052 compatible = "fixed-clock";
0053 #clock-cells = <0>;
0054 clock-frequency = <0>;
0055 clock-output-names = "enet_rx_clk";
0056 };
0057
0058 enet_tx_clk: enet_tx_clk {
0059 compatible = "fixed-clock";
0060 #clock-cells = <0>;
0061 clock-frequency = <0>;
0062 clock-output-names = "enet_tx_clk";
0063 };
0064
0065 gp_clkin: gp_clkin {
0066 compatible = "fixed-clock";
0067 #clock-cells = <0>;
0068 clock-frequency = <0>;
0069 clock-output-names = "gp_clkin";
0070 };
0071 };
0072
0073 soc {
0074 sct_pwm: pwm@40000000 {
0075 compatible = "nxp,lpc1850-sct-pwm";
0076 reg = <0x40000000 0x1000>;
0077 clocks =<&ccu1 CLK_CPU_SCT>;
0078 clock-names = "pwm";
0079 resets = <&rgu 37>;
0080 #pwm-cells = <3>;
0081 status = "disabled";
0082 };
0083
0084 dmac: dma-controller@40002000 {
0085 compatible = "arm,pl080", "arm,primecell";
0086 arm,primecell-periphid = <0x00041080>;
0087 reg = <0x40002000 0x1000>;
0088 interrupts = <2>;
0089 clocks = <&ccu1 CLK_CPU_DMA>;
0090 clock-names = "apb_pclk";
0091 resets = <&rgu 19>;
0092 #dma-cells = <2>;
0093 dma-channels = <8>;
0094 dma-requests = <16>;
0095 lli-bus-interface-ahb1;
0096 lli-bus-interface-ahb2;
0097 mem-bus-interface-ahb1;
0098 mem-bus-interface-ahb2;
0099 memcpy-burst-size = <256>;
0100 memcpy-bus-width = <32>;
0101 };
0102
0103 spifi: flash-controller@40003000 {
0104 compatible = "nxp,lpc1773-spifi";
0105 reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
0106 reg-names = "spifi", "flash";
0107 interrupts = <30>;
0108 clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
0109 clock-names = "spifi", "reg";
0110 resets = <&rgu 53>;
0111 status = "disabled";
0112 };
0113
0114 mmcsd: mmcsd@40004000 {
0115 compatible = "snps,dw-mshc";
0116 reg = <0x40004000 0x1000>;
0117 interrupts = <6>;
0118 clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
0119 clock-names = "ciu", "biu";
0120 resets = <&rgu 20>;
0121 status = "disabled";
0122 };
0123
0124 usb0: usb@40006100 {
0125 compatible = "nxp,lpc1850-ehci", "generic-ehci";
0126 reg = <0x40006100 0x100>;
0127 interrupts = <8>;
0128 clocks = <&ccu1 CLK_CPU_USB0>;
0129 resets = <&rgu 17>;
0130 phys = <&usb0_otg_phy>;
0131 phy-names = "usb";
0132 has-transaction-translator;
0133 status = "disabled";
0134 };
0135
0136 usb1: usb@40007100 {
0137 compatible = "nxp,lpc1850-ehci", "generic-ehci";
0138 reg = <0x40007100 0x100>;
0139 interrupts = <9>;
0140 clocks = <&ccu1 CLK_CPU_USB1>;
0141 resets = <&rgu 18>;
0142 status = "disabled";
0143 };
0144
0145 emc: memory-controller@40005000 {
0146 compatible = "arm,pl172", "arm,primecell";
0147 reg = <0x40005000 0x1000>;
0148 clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
0149 clock-names = "mpmcclk", "apb_pclk";
0150 resets = <&rgu 21>;
0151 #address-cells = <2>;
0152 #size-cells = <1>;
0153 ranges = <0 0 0x1c000000 0x1000000
0154 1 0 0x1d000000 0x1000000
0155 2 0 0x1e000000 0x1000000
0156 3 0 0x1f000000 0x1000000>;
0157 status = "disabled";
0158 };
0159
0160 lcdc: lcd-controller@40008000 {
0161 compatible = "arm,pl111", "arm,primecell";
0162 reg = <0x40008000 0x1000>;
0163 interrupts = <7>;
0164 interrupt-names = "combined";
0165 clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
0166 clock-names = "clcdclk", "apb_pclk";
0167 resets = <&rgu 16>;
0168 status = "disabled";
0169 };
0170
0171 eeprom: eeprom@4000e000 {
0172 compatible = "nxp,lpc1857-eeprom";
0173 reg = <0x4000e000 0x1000>, <0x20040000 0x4000>;
0174 reg-names = "reg", "mem";
0175 clocks = <&ccu1 CLK_CPU_EEPROM>;
0176 clock-names = "eeprom";
0177 resets = <&rgu 27>;
0178 interrupts = <4>;
0179 status = "disabled";
0180 };
0181
0182 mac: ethernet@40010000 {
0183 compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
0184 reg = <0x40010000 0x2000>;
0185 interrupts = <5>;
0186 interrupt-names = "macirq";
0187 clocks = <&ccu1 CLK_CPU_ETHERNET>;
0188 clock-names = "stmmaceth";
0189 resets = <&rgu 22>;
0190 reset-names = "stmmaceth";
0191 rx-fifo-depth = <256>;
0192 tx-fifo-depth = <256>;
0193 snps,pbl = <4>; /* 32 (8x mode) */
0194 snps,force_thresh_dma_mode;
0195 status = "disabled";
0196 };
0197
0198 creg: syscon@40043000 {
0199 compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
0200 reg = <0x40043000 0x1000>;
0201 clocks = <&ccu1 CLK_CPU_CREG>;
0202 resets = <&rgu 5>;
0203
0204 creg_clk: clock-controller {
0205 compatible = "nxp,lpc1850-creg-clk";
0206 clocks = <&xtal32>;
0207 #clock-cells = <1>;
0208 };
0209
0210 usb0_otg_phy: phy {
0211 compatible = "nxp,lpc1850-usb-otg-phy";
0212 clocks = <&ccu1 CLK_USB0>;
0213 #phy-cells = <0>;
0214 };
0215
0216 dmamux: dma-mux {
0217 compatible = "nxp,lpc1850-dmamux";
0218 #dma-cells = <3>;
0219 dma-requests = <64>;
0220 dma-masters = <&dmac>;
0221 };
0222 };
0223
0224 rtc: rtc@40046000 {
0225 compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc";
0226 reg = <0x40046000 0x1000>;
0227 interrupts = <47>;
0228 clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
0229 clock-names = "rtc", "reg";
0230 };
0231
0232 cgu: clock-controller@40050000 {
0233 compatible = "nxp,lpc1850-cgu";
0234 reg = <0x40050000 0x1000>;
0235 #clock-cells = <1>;
0236 clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
0237 };
0238
0239 ccu1: clock-controller@40051000 {
0240 compatible = "nxp,lpc1850-ccu";
0241 reg = <0x40051000 0x1000>;
0242 #clock-cells = <1>;
0243 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
0244 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
0245 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
0246 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
0247 clock-names = "base_apb3_clk", "base_apb1_clk",
0248 "base_spifi_clk", "base_cpu_clk",
0249 "base_periph_clk", "base_usb0_clk",
0250 "base_usb1_clk", "base_spi_clk";
0251 };
0252
0253 ccu2: clock-controller@40052000 {
0254 compatible = "nxp,lpc1850-ccu";
0255 reg = <0x40052000 0x1000>;
0256 #clock-cells = <1>;
0257 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
0258 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
0259 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
0260 <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
0261 clock-names = "base_audio_clk", "base_uart3_clk",
0262 "base_uart2_clk", "base_uart1_clk",
0263 "base_uart0_clk", "base_ssp1_clk",
0264 "base_ssp0_clk", "base_sdio_clk";
0265 };
0266
0267 rgu: reset-controller@40053000 {
0268 compatible = "nxp,lpc1850-rgu";
0269 reg = <0x40053000 0x1000>;
0270 clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
0271 clock-names = "delay", "reg";
0272 #reset-cells = <1>;
0273 };
0274
0275 watchdog@40080000 {
0276 compatible = "nxp,lpc1850-wwdt";
0277 reg = <0x40080000 0x24>;
0278 interrupts = <49>;
0279 clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>;
0280 clock-names = "wdtclk", "reg";
0281 };
0282
0283 uart0: serial@40081000 {
0284 compatible = "nxp,lpc1850-uart", "ns16550a";
0285 reg = <0x40081000 0x1000>;
0286 reg-shift = <2>;
0287 interrupts = <24>;
0288 clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
0289 clock-names = "uartclk", "reg";
0290 resets = <&rgu 44>;
0291 dmas = <&dmamux 1 1 2
0292 &dmamux 2 1 2
0293 &dmamux 11 2 2
0294 &dmamux 12 2 2>;
0295 dma-names = "tx", "rx", "tx", "rx";
0296 status = "disabled";
0297 };
0298
0299 uart1: serial@40082000 {
0300 compatible = "nxp,lpc1850-uart", "ns16550a";
0301 reg = <0x40082000 0x1000>;
0302 reg-shift = <2>;
0303 interrupts = <25>;
0304 clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
0305 clock-names = "uartclk", "reg";
0306 resets = <&rgu 45>;
0307 dmas = <&dmamux 3 1 2
0308 &dmamux 4 1 2>;
0309 dma-names = "tx", "rx";
0310 status = "disabled";
0311 };
0312
0313 ssp0: spi@40083000 {
0314 compatible = "arm,pl022", "arm,primecell";
0315 reg = <0x40083000 0x1000>;
0316 interrupts = <22>;
0317 clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;
0318 clock-names = "sspclk", "apb_pclk";
0319 resets = <&rgu 50>;
0320 dmas = <&dmamux 9 0 2
0321 &dmamux 10 0 2>;
0322 dma-names = "rx", "tx";
0323 #address-cells = <1>;
0324 #size-cells = <0>;
0325 status = "disabled";
0326 };
0327
0328 timer0: timer@40084000 {
0329 compatible = "nxp,lpc3220-timer";
0330 reg = <0x40084000 0x1000>;
0331 interrupts = <12>;
0332 clocks = <&ccu1 CLK_CPU_TIMER0>;
0333 clock-names = "timerclk";
0334 resets = <&rgu 32>;
0335 };
0336
0337 timer1: timer@40085000 {
0338 compatible = "nxp,lpc3220-timer";
0339 reg = <0x40085000 0x1000>;
0340 interrupts = <13>;
0341 clocks = <&ccu1 CLK_CPU_TIMER1>;
0342 clock-names = "timerclk";
0343 resets = <&rgu 33>;
0344 };
0345
0346 pinctrl: pinctrl@40086000 {
0347 compatible = "nxp,lpc1850-scu";
0348 reg = <0x40086000 0x1000>;
0349 clocks = <&ccu1 CLK_CPU_SCU>;
0350 };
0351
0352 i2c0: i2c@400a1000 {
0353 compatible = "nxp,lpc1788-i2c";
0354 reg = <0x400a1000 0x1000>;
0355 interrupts = <18>;
0356 clocks = <&ccu1 CLK_APB1_I2C0>;
0357 resets = <&rgu 48>;
0358 #address-cells = <1>;
0359 #size-cells = <0>;
0360 status = "disabled";
0361 };
0362
0363 can1: can@400a4000 {
0364 compatible = "bosch,c_can";
0365 reg = <0x400a4000 0x1000>;
0366 interrupts = <43>;
0367 clocks = <&ccu1 CLK_APB1_CAN1>;
0368 resets = <&rgu 54>;
0369 status = "disabled";
0370 };
0371
0372 uart2: serial@400c1000 {
0373 compatible = "nxp,lpc1850-uart", "ns16550a";
0374 reg = <0x400c1000 0x1000>;
0375 reg-shift = <2>;
0376 interrupts = <26>;
0377 clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;
0378 clock-names = "uartclk", "reg";
0379 resets = <&rgu 46>;
0380 dmas = <&dmamux 5 1 2
0381 &dmamux 6 1 2>;
0382 dma-names = "tx", "rx";
0383 status = "disabled";
0384 };
0385
0386 uart3: serial@400c2000 {
0387 compatible = "nxp,lpc1850-uart", "ns16550a";
0388 reg = <0x400c2000 0x1000>;
0389 reg-shift = <2>;
0390 interrupts = <27>;
0391 clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;
0392 clock-names = "uartclk", "reg";
0393 resets = <&rgu 47>;
0394 dmas = <&dmamux 7 1 2
0395 &dmamux 8 1 2
0396 &dmamux 13 3 2
0397 &dmamux 14 3 2>;
0398 dma-names = "tx", "rx", "rx", "tx";
0399 status = "disabled";
0400 };
0401
0402 timer2: timer@400c3000 {
0403 compatible = "nxp,lpc3220-timer";
0404 reg = <0x400c3000 0x1000>;
0405 interrupts = <14>;
0406 clocks = <&ccu1 CLK_CPU_TIMER2>;
0407 clock-names = "timerclk";
0408 resets = <&rgu 34>;
0409 };
0410
0411 timer3: timer@400c4000 {
0412 compatible = "nxp,lpc3220-timer";
0413 reg = <0x400c4000 0x1000>;
0414 interrupts = <15>;
0415 clocks = <&ccu1 CLK_CPU_TIMER3>;
0416 clock-names = "timerclk";
0417 resets = <&rgu 35>;
0418 };
0419
0420 ssp1: spi@400c5000 {
0421 compatible = "arm,pl022", "arm,primecell";
0422 reg = <0x400c5000 0x1000>;
0423 interrupts = <23>;
0424 clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;
0425 clock-names = "sspclk", "apb_pclk";
0426 resets = <&rgu 51>;
0427 dmas = <&dmamux 11 2 2
0428 &dmamux 12 2 2
0429 &dmamux 3 3 2
0430 &dmamux 4 3 2
0431 &dmamux 5 2 2
0432 &dmamux 6 2 2
0433 &dmamux 13 2 2
0434 &dmamux 14 2 2>;
0435 dma-names = "rx", "tx", "tx", "rx",
0436 "tx", "rx", "rx", "tx";
0437 #address-cells = <1>;
0438 #size-cells = <0>;
0439 status = "disabled";
0440 };
0441
0442 i2c1: i2c@400e0000 {
0443 compatible = "nxp,lpc1788-i2c";
0444 reg = <0x400e0000 0x1000>;
0445 interrupts = <19>;
0446 clocks = <&ccu1 CLK_APB3_I2C1>;
0447 resets = <&rgu 49>;
0448 #address-cells = <1>;
0449 #size-cells = <0>;
0450 status = "disabled";
0451 };
0452
0453 dac: dac@400e1000 {
0454 compatible = "nxp,lpc1850-dac";
0455 reg = <0x400e1000 0x1000>;
0456 interrupts = <0>;
0457 clocks = <&ccu1 CLK_APB3_DAC>;
0458 resets = <&rgu 42>;
0459 status = "disabled";
0460 };
0461
0462 can0: can@400e2000 {
0463 compatible = "bosch,c_can";
0464 reg = <0x400e2000 0x1000>;
0465 interrupts = <51>;
0466 clocks = <&ccu1 CLK_APB3_CAN0>;
0467 resets = <&rgu 55>;
0468 status = "disabled";
0469 };
0470
0471 adc0: adc@400e3000 {
0472 compatible = "nxp,lpc1850-adc";
0473 reg = <0x400e3000 0x1000>;
0474 interrupts = <17>;
0475 clocks = <&ccu1 CLK_APB3_ADC0>;
0476 resets = <&rgu 40>;
0477 status = "disabled";
0478 };
0479
0480 adc1: adc@400e4000 {
0481 compatible = "nxp,lpc1850-adc";
0482 reg = <0x400e4000 0x1000>;
0483 interrupts = <21>;
0484 clocks = <&ccu1 CLK_APB3_ADC1>;
0485 resets = <&rgu 41>;
0486 status = "disabled";
0487 };
0488
0489 gpio: gpio@400f4000 {
0490 compatible = "nxp,lpc1850-gpio";
0491 reg = <0x400f4000 0x4000>;
0492 clocks = <&ccu1 CLK_CPU_GPIO>;
0493 gpio-controller;
0494 #gpio-cells = <2>;
0495 gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>,
0496 <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>,
0497 <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>,
0498 <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>,
0499 <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>,
0500 <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>,
0501 <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,
0502 <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,
0503 <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>,
0504 <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>,
0505 <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>,
0506 <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>,
0507 <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,
0508 <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,
0509 <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>,
0510 <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>,
0511 <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>,
0512 <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>,
0513 <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>,
0514 <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>,
0515 <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>,
0516 <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>,
0517 <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>,
0518 <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>,
0519 <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>,
0520 <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>,
0521 <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>,
0522 <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>,
0523 <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>,
0524 <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>,
0525 <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>,
0526 <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>,
0527 <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>,
0528 <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>,
0529 <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>,
0530 <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>,
0531 <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,
0532 <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>,
0533 <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>,
0534 <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>;
0535 };
0536 };
0537 };
