0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
0004 *
0005 * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
0006 *
0007 * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
0008 *
0009 */
0010
0011 #include <dt-bindings/interrupt-controller/irq.h>
0012 #include <dt-bindings/interrupt-controller/arm-gic.h>
0013 #include <dt-bindings/mfd/atmel-flexcom.h>
0014 #include <dt-bindings/dma/at91.h>
0015 #include <dt-bindings/gpio/gpio.h>
0016 #include <dt-bindings/clock/microchip,lan966x.h>
0017
0018 / {
0019 model = "Microchip LAN966 family SoC";
0020 compatible = "microchip,lan966";
0021 interrupt-parent = <&gic>;
0022 #address-cells = <1>;
0023 #size-cells = <1>;
0024
0025 cpus {
0026 #address-cells = <1>;
0027 #size-cells = <0>;
0028
0029 cpu@0 {
0030 device_type = "cpu";
0031 compatible = "arm,cortex-a7";
0032 clock-frequency = <600000000>;
0033 reg = <0x0>;
0034 };
0035 };
0036
0037 clocks {
0038 sys_clk: sys_clk {
0039 compatible = "fixed-clock";
0040 #clock-cells = <0>;
0041 clock-frequency = <165625000>;
0042 };
0043
0044 cpu_clk: cpu_clk {
0045 compatible = "fixed-clock";
0046 #clock-cells = <0>;
0047 clock-frequency = <600000000>;
0048 };
0049
0050 ddr_clk: ddr_clk {
0051 compatible = "fixed-clock";
0052 #clock-cells = <0>;
0053 clock-frequency = <300000000>;
0054 };
0055
0056 nic_clk: nic_clk {
0057 compatible = "fixed-clock";
0058 #clock-cells = <0>;
0059 clock-frequency = <200000000>;
0060 };
0061 };
0062
0063 clks: clock-controller@e00c00a8 {
0064 compatible = "microchip,lan966x-gck";
0065 #clock-cells = <1>;
0066 clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
0067 clock-names = "cpu", "ddr", "sys";
0068 reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>;
0069 };
0070
0071 timer {
0072 compatible = "arm,armv7-timer";
0073 interrupt-parent = <&gic>;
0074 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0075 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0076 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0077 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
0078 clock-frequency = <37500000>;
0079 };
0080
0081 soc {
0082 compatible = "simple-bus";
0083 #address-cells = <1>;
0084 #size-cells = <1>;
0085 ranges;
0086
0087 udc: usb@200000 {
0088 compatible = "microchip,lan9662-udc",
0089 "atmel,sama5d3-udc";
0090 reg = <0x00200000 0x80000>,
0091 <0xe0808000 0x400>;
0092 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0093 clocks = <&clks GCK_GATE_UDPHS>, <&nic_clk>;
0094 clock-names = "pclk", "hclk";
0095 status = "disabled";
0096 };
0097
0098 switch: switch@e0000000 {
0099 compatible = "microchip,lan966x-switch";
0100 reg = <0xe0000000 0x0100000>,
0101 <0xe2000000 0x0800000>;
0102 reg-names = "cpu", "gcb";
0103 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0104 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0105 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0106 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0107 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0108 interrupt-names = "xtr", "fdma", "ana", "ptp",
0109 "ptp-ext";
0110 resets = <&reset 0>;
0111 reset-names = "switch";
0112 status = "disabled";
0113
0114 ethernet-ports {
0115 #address-cells = <1>;
0116 #size-cells = <0>;
0117
0118 port0: port@0 {
0119 reg = <0>;
0120 status = "disabled";
0121 };
0122
0123 port1: port@1 {
0124 reg = <1>;
0125 status = "disabled";
0126 };
0127
0128 port2: port@2 {
0129 reg = <2>;
0130 status = "disabled";
0131 };
0132
0133 port3: port@3 {
0134 reg = <3>;
0135 status = "disabled";
0136 };
0137
0138 port4: port@4 {
0139 reg = <4>;
0140 status = "disabled";
0141 };
0142
0143 port5: port@5 {
0144 reg = <5>;
0145 status = "disabled";
0146 };
0147
0148 port6: port@6 {
0149 reg = <6>;
0150 status = "disabled";
0151 };
0152
0153 port7: port@7 {
0154 reg = <7>;
0155 status = "disabled";
0156 };
0157 };
0158 };
0159
0160 flx0: flexcom@e0040000 {
0161 compatible = "atmel,sama5d2-flexcom";
0162 reg = <0xe0040000 0x100>;
0163 clocks = <&clks GCK_ID_FLEXCOM0>;
0164 #address-cells = <1>;
0165 #size-cells = <1>;
0166 ranges = <0x0 0xe0040000 0x800>;
0167 status = "disabled";
0168
0169 usart0: serial@200 {
0170 compatible = "atmel,at91sam9260-usart";
0171 reg = <0x200 0x200>;
0172 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0173 dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
0174 <&dma0 AT91_XDMAC_DT_PERID(2)>;
0175 dma-names = "tx", "rx";
0176 clocks = <&nic_clk>;
0177 clock-names = "usart";
0178 atmel,fifo-size = <32>;
0179 status = "disabled";
0180 };
0181
0182 spi0: spi@400 {
0183 compatible = "atmel,at91rm9200-spi";
0184 reg = <0x400 0x200>;
0185 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0186 dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
0187 <&dma0 AT91_XDMAC_DT_PERID(2)>;
0188 dma-names = "tx", "rx";
0189 clocks = <&nic_clk>;
0190 clock-names = "spi_clk";
0191 atmel,fifo-size = <32>;
0192 #address-cells = <1>;
0193 #size-cells = <0>;
0194 status = "disabled";
0195 };
0196
0197 i2c0: i2c@600 {
0198 compatible = "microchip,sam9x60-i2c";
0199 reg = <0x600 0x200>;
0200 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0201 dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
0202 <&dma0 AT91_XDMAC_DT_PERID(2)>;
0203 dma-names = "tx", "rx";
0204 clocks = <&nic_clk>;
0205 #address-cells = <1>;
0206 #size-cells = <0>;
0207 status = "disabled";
0208 };
0209 };
0210
0211 flx1: flexcom@e0044000 {
0212 compatible = "atmel,sama5d2-flexcom";
0213 reg = <0xe0044000 0x100>;
0214 clocks = <&clks GCK_ID_FLEXCOM1>;
0215 #address-cells = <1>;
0216 #size-cells = <1>;
0217 ranges = <0x0 0xe0044000 0x800>;
0218 status = "disabled";
0219
0220 usart1: serial@200 {
0221 compatible = "atmel,at91sam9260-usart";
0222 reg = <0x200 0x200>;
0223 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0224 dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
0225 <&dma0 AT91_XDMAC_DT_PERID(4)>;
0226 dma-names = "tx", "rx";
0227 clocks = <&nic_clk>;
0228 clock-names = "usart";
0229 atmel,fifo-size = <32>;
0230 status = "disabled";
0231 };
0232
0233 spi1: spi@400 {
0234 compatible = "atmel,at91rm9200-spi";
0235 reg = <0x400 0x200>;
0236 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0237 dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
0238 <&dma0 AT91_XDMAC_DT_PERID(4)>;
0239 dma-names = "tx", "rx";
0240 clocks = <&nic_clk>;
0241 clock-names = "spi_clk";
0242 atmel,fifo-size = <32>;
0243 #address-cells = <1>;
0244 #size-cells = <0>;
0245 status = "disabled";
0246 };
0247
0248 i2c1: i2c@600 {
0249 compatible = "microchip,sam9x60-i2c";
0250 reg = <0x600 0x200>;
0251 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0252 dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
0253 <&dma0 AT91_XDMAC_DT_PERID(4)>;
0254 dma-names = "tx", "rx";
0255 clocks = <&nic_clk>;
0256 #address-cells = <1>;
0257 #size-cells = <0>;
0258 status = "disabled";
0259 };
0260 };
0261
0262 trng: rng@e0048000 {
0263 compatible = "atmel,at91sam9g45-trng";
0264 reg = <0xe0048000 0x100>;
0265 clocks = <&nic_clk>;
0266 };
0267
0268 aes: crypto@e004c000 {
0269 compatible = "atmel,at91sam9g46-aes";
0270 reg = <0xe004c000 0x100>;
0271 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0272 dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>,
0273 <&dma0 AT91_XDMAC_DT_PERID(13)>;
0274 dma-names = "tx", "rx";
0275 clocks = <&nic_clk>;
0276 clock-names = "aes_clk";
0277 };
0278
0279 flx2: flexcom@e0060000 {
0280 compatible = "atmel,sama5d2-flexcom";
0281 reg = <0xe0060000 0x100>;
0282 clocks = <&clks GCK_ID_FLEXCOM2>;
0283 #address-cells = <1>;
0284 #size-cells = <1>;
0285 ranges = <0x0 0xe0060000 0x800>;
0286 status = "disabled";
0287
0288 usart2: serial@200 {
0289 compatible = "atmel,at91sam9260-usart";
0290 reg = <0x200 0x200>;
0291 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0292 dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
0293 <&dma0 AT91_XDMAC_DT_PERID(6)>;
0294 dma-names = "tx", "rx";
0295 clocks = <&nic_clk>;
0296 clock-names = "usart";
0297 atmel,fifo-size = <32>;
0298 status = "disabled";
0299 };
0300
0301 spi2: spi@400 {
0302 compatible = "atmel,at91rm9200-spi";
0303 reg = <0x400 0x200>;
0304 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0305 dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
0306 <&dma0 AT91_XDMAC_DT_PERID(6)>;
0307 dma-names = "tx", "rx";
0308 clocks = <&nic_clk>;
0309 clock-names = "spi_clk";
0310 atmel,fifo-size = <32>;
0311 #address-cells = <1>;
0312 #size-cells = <0>;
0313 status = "disabled";
0314 };
0315
0316 i2c2: i2c@600 {
0317 compatible = "microchip,sam9x60-i2c";
0318 reg = <0x600 0x200>;
0319 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0320 dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
0321 <&dma0 AT91_XDMAC_DT_PERID(6)>;
0322 dma-names = "tx", "rx";
0323 clocks = <&nic_clk>;
0324 #address-cells = <1>;
0325 #size-cells = <0>;
0326 status = "disabled";
0327 };
0328 };
0329
0330 flx3: flexcom@e0064000 {
0331 compatible = "atmel,sama5d2-flexcom";
0332 reg = <0xe0064000 0x100>;
0333 clocks = <&clks GCK_ID_FLEXCOM3>;
0334 #address-cells = <1>;
0335 #size-cells = <1>;
0336 ranges = <0x0 0xe0064000 0x800>;
0337 status = "disabled";
0338
0339 usart3: serial@200 {
0340 compatible = "atmel,at91sam9260-usart";
0341 reg = <0x200 0x200>;
0342 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0343 dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
0344 <&dma0 AT91_XDMAC_DT_PERID(8)>;
0345 dma-names = "tx", "rx";
0346 clocks = <&nic_clk>;
0347 clock-names = "usart";
0348 atmel,fifo-size = <32>;
0349 status = "disabled";
0350 };
0351
0352 spi3: spi@400 {
0353 compatible = "atmel,at91rm9200-spi";
0354 reg = <0x400 0x200>;
0355 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0356 dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
0357 <&dma0 AT91_XDMAC_DT_PERID(8)>;
0358 dma-names = "tx", "rx";
0359 clocks = <&nic_clk>;
0360 clock-names = "spi_clk";
0361 atmel,fifo-size = <32>;
0362 #address-cells = <1>;
0363 #size-cells = <0>;
0364 status = "disabled";
0365 };
0366
0367 i2c3: i2c@600 {
0368 compatible = "microchip,sam9x60-i2c";
0369 reg = <0x600 0x200>;
0370 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0371 dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
0372 <&dma0 AT91_XDMAC_DT_PERID(8)>;
0373 dma-names = "tx", "rx";
0374 clocks = <&nic_clk>;
0375 #address-cells = <1>;
0376 #size-cells = <0>;
0377 status = "disabled";
0378 };
0379 };
0380
0381 dma0: dma-controller@e0068000 {
0382 compatible = "microchip,sama7g5-dma";
0383 reg = <0xe0068000 0x1000>;
0384 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
0385 #dma-cells = <1>;
0386 clocks = <&nic_clk>;
0387 clock-names = "dma_clk";
0388 };
0389
0390 sha: crypto@e006c000 {
0391 compatible = "atmel,at91sam9g46-sha";
0392 reg = <0xe006c000 0xec>;
0393 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0394 dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>;
0395 dma-names = "tx";
0396 clocks = <&nic_clk>;
0397 clock-names = "sha_clk";
0398 };
0399
0400 flx4: flexcom@e0070000 {
0401 compatible = "atmel,sama5d2-flexcom";
0402 reg = <0xe0070000 0x100>;
0403 clocks = <&clks GCK_ID_FLEXCOM4>;
0404 #address-cells = <1>;
0405 #size-cells = <1>;
0406 ranges = <0x0 0xe0070000 0x800>;
0407 status = "disabled";
0408
0409 usart4: serial@200 {
0410 compatible = "atmel,at91sam9260-usart";
0411 reg = <0x200 0x200>;
0412 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
0413 dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
0414 <&dma0 AT91_XDMAC_DT_PERID(10)>;
0415 dma-names = "tx", "rx";
0416 clocks = <&nic_clk>;
0417 clock-names = "usart";
0418 atmel,fifo-size = <32>;
0419 status = "disabled";
0420 };
0421
0422 spi4: spi@400 {
0423 compatible = "atmel,at91rm9200-spi";
0424 reg = <0x400 0x200>;
0425 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
0426 dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
0427 <&dma0 AT91_XDMAC_DT_PERID(10)>;
0428 dma-names = "tx", "rx";
0429 clocks = <&nic_clk>;
0430 clock-names = "spi_clk";
0431 atmel,fifo-size = <32>;
0432 #address-cells = <1>;
0433 #size-cells = <0>;
0434 status = "disabled";
0435 };
0436
0437 i2c4: i2c@600 {
0438 compatible = "microchip,sam9x60-i2c";
0439 reg = <0x600 0x200>;
0440 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
0441 dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
0442 <&dma0 AT91_XDMAC_DT_PERID(10)>;
0443 dma-names = "tx", "rx";
0444 clocks = <&nic_clk>;
0445 #address-cells = <1>;
0446 #size-cells = <0>;
0447 status = "disabled";
0448 };
0449 };
0450
0451 timer0: timer@e008c000 {
0452 compatible = "snps,dw-apb-timer";
0453 reg = <0xe008c000 0x400>;
0454 clocks = <&nic_clk>;
0455 clock-names = "timer";
0456 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0457 };
0458
0459 watchdog: watchdog@e0090000 {
0460 compatible = "snps,dw-wdt";
0461 reg = <0xe0090000 0x1000>;
0462 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0463 clocks = <&nic_clk>;
0464 status = "disabled";
0465 };
0466
0467 cpu_ctrl: syscon@e00c0000 {
0468 compatible = "microchip,lan966x-cpu-syscon", "syscon";
0469 reg = <0xe00c0000 0x350>;
0470 };
0471
0472 can0: can@e081c000 {
0473 compatible = "bosch,m_can";
0474 reg = <0xe081c000 0xfc>, <0x00100000 0x4000>;
0475 reg-names = "m_can", "message_ram";
0476 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
0477 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0478 interrupt-names = "int0", "int1";
0479 clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>;
0480 clock-names = "hclk", "cclk";
0481 assigned-clocks = <&clks GCK_ID_MCAN0>;
0482 assigned-clock-rates = <40000000>;
0483 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
0484 status = "disabled";
0485 };
0486
0487 can1: can@e0820000 {
0488 compatible = "bosch,m_can";
0489 reg = <0xe0820000 0xfc>, <0x00100000 0x8000>;
0490 reg-names = "m_can", "message_ram";
0491 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
0492 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0493 interrupt-names = "int0", "int1";
0494 clocks = <&clks GCK_ID_MCAN1>, <&clks GCK_ID_MCAN1>;
0495 clock-names = "hclk", "cclk";
0496 assigned-clocks = <&clks GCK_ID_MCAN1>;
0497 assigned-clock-rates = <40000000>;
0498 bosch,mram-cfg = <0x4000 0 0 64 0 0 32 32>;
0499 status = "disabled";
0500 };
0501
0502 reset: reset-controller@e200400c {
0503 compatible = "microchip,lan966x-switch-reset";
0504 reg = <0xe200400c 0x4>;
0505 reg-names = "gcb";
0506 #reset-cells = <1>;
0507 cpu-syscon = <&cpu_ctrl>;
0508 };
0509
0510 gpio: pinctrl@e2004064 {
0511 compatible = "microchip,lan966x-pinctrl";
0512 reg = <0xe2004064 0xb4>,
0513 <0xe2010024 0x138>;
0514 resets = <&reset 0>;
0515 reset-names = "switch";
0516 gpio-controller;
0517 #gpio-cells = <2>;
0518 gpio-ranges = <&gpio 0 0 78>;
0519 interrupt-controller;
0520 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0521 #interrupt-cells = <2>;
0522 };
0523
0524 mdio0: mdio@e2004118 {
0525 compatible = "microchip,lan966x-miim";
0526 #address-cells = <1>;
0527 #size-cells = <0>;
0528 reg = <0xe2004118 0x24>;
0529 clocks = <&sys_clk>;
0530 status = "disabled";
0531 };
0532
0533 mdio1: mdio@e200413c {
0534 compatible = "microchip,lan966x-miim";
0535 #address-cells = <1>;
0536 #size-cells = <0>;
0537 reg = <0xe200413c 0x24>,
0538 <0xe2010020 0x4>;
0539 clocks = <&sys_clk>;
0540 status = "disabled";
0541
0542 phy0: ethernet-phy@1 {
0543 reg = <1>;
0544 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0545 status = "disabled";
0546 };
0547
0548 phy1: ethernet-phy@2 {
0549 reg = <2>;
0550 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0551 status = "disabled";
0552 };
0553 };
0554
0555 sgpio: gpio@e2004190 {
0556 compatible = "microchip,sparx5-sgpio";
0557 reg = <0xe2004190 0x118>;
0558 clocks = <&sys_clk>;
0559 resets = <&reset 0>;
0560 reset-names = "switch";
0561 #address-cells = <1>;
0562 #size-cells = <0>;
0563 status = "disabled";
0564
0565 sgpio_in: gpio@0 {
0566 compatible = "microchip,sparx5-sgpio-bank";
0567 reg = <0>;
0568 gpio-controller;
0569 #gpio-cells = <3>;
0570 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0571 interrupt-controller;
0572 #interrupt-cells = <3>;
0573 };
0574
0575 sgpio_out: gpio@1 {
0576 compatible = "microchip,sparx5-sgpio-bank";
0577 reg = <1>;
0578 gpio-controller;
0579 #gpio-cells = <3>;
0580 };
0581 };
0582
0583 hwmon: hwmon@e2010180 {
0584 compatible = "microchip,lan9668-hwmon";
0585 reg = <0xe2010180 0xc>,
0586 <0xe20042a8 0xc>;
0587 reg-names = "pvt", "fan";
0588 clocks = <&sys_clk>;
0589 };
0590
0591 serdes: serdes@e202c000 {
0592 compatible = "microchip,lan966x-serdes";
0593 reg = <0xe202c000 0x9c>,
0594 <0xe2004010 0x4>;
0595 #phy-cells = <2>;
0596 status = "disabled";
0597 };
0598
0599 gic: interrupt-controller@e8c11000 {
0600 compatible = "arm,gic-400", "arm,cortex-a7-gic";
0601 #interrupt-cells = <3>;
0602 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0603 interrupt-controller;
0604 reg = <0xe8c11000 0x1000>,
0605 <0xe8c12000 0x2000>,
0606 <0xe8c14000 0x2000>,
0607 <0xe8c16000 0x2000>;
0608 };
0609 };
0610 };
