0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <dt-bindings/input/input.h>
0003 #include <dt-bindings/gpio/gpio.h>
0004
0005 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
0006
0007 / {
0008 #address-cells = <1>;
0009 #size-cells = <1>;
0010 compatible = "marvell,kirkwood";
0011 interrupt-parent = <&intc>;
0012
0013 cpus {
0014 #address-cells = <1>;
0015 #size-cells = <0>;
0016
0017 cpu@0 {
0018 device_type = "cpu";
0019 compatible = "marvell,feroceon";
0020 reg = <0>;
0021 clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
0022 clock-names = "cpu_clk", "ddrclk", "powersave";
0023 };
0024 };
0025
0026 aliases {
0027 gpio0 = &gpio0;
0028 gpio1 = &gpio1;
0029 i2c0 = &i2c0;
0030 };
0031
0032 mbus@f1000000 {
0033 compatible = "marvell,kirkwood-mbus", "simple-bus";
0034 #address-cells = <2>;
0035 #size-cells = <1>;
0036 /* If a board file needs to change this ranges it must replace it completely */
0037 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
0038 MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
0039 MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
0040 >;
0041 controller = <&mbusc>;
0042 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
0043 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
0044
0045 nand: nand@12f {
0046 #address-cells = <1>;
0047 #size-cells = <1>;
0048 cle = <0>;
0049 ale = <1>;
0050 bank-width = <1>;
0051 compatible = "marvell,orion-nand";
0052 reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
0053 chip-delay = <25>;
0054 /* set partition map and/or chip-delay in board dts */
0055 clocks = <&gate_clk 7>;
0056 pinctrl-0 = <&pmx_nand>;
0057 pinctrl-names = "default";
0058 status = "disabled";
0059 };
0060
0061 crypto_sram: sa-sram@301 {
0062 compatible = "mmio-sram";
0063 reg = <MBUS_ID(0x03, 0x01) 0x0 0x800>;
0064 clocks = <&gate_clk 17>;
0065 #address-cells = <1>;
0066 #size-cells = <1>;
0067 };
0068 };
0069
0070 ocp@f1000000 {
0071 compatible = "simple-bus";
0072 ranges = <0x00000000 0xf1000000 0x0100000>;
0073 #address-cells = <1>;
0074 #size-cells = <1>;
0075
0076 pinctrl: pin-controller@10000 {
0077 /* set compatible property in SoC file */
0078 reg = <0x10000 0x20>;
0079
0080 pmx_ge1: pmx-ge1 {
0081 marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23",
0082 "mpp24", "mpp25", "mpp26", "mpp27",
0083 "mpp30", "mpp31", "mpp32", "mpp33";
0084 marvell,function = "ge1";
0085 };
0086
0087 pmx_nand: pmx-nand {
0088 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
0089 "mpp4", "mpp5", "mpp18", "mpp19";
0090 marvell,function = "nand";
0091 };
0092
0093 /*
0094 * Default SPI0 pinctrl setting with CSn on mpp0,
0095 * overwrite marvell,pins on board level if required.
0096 */
0097 pmx_spi: pmx-spi {
0098 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
0099 marvell,function = "spi";
0100 };
0101
0102 pmx_twsi0: pmx-twsi0 {
0103 marvell,pins = "mpp8", "mpp9";
0104 marvell,function = "twsi0";
0105 };
0106
0107 /*
0108 * Default UART pinctrl setting without RTS/CTS,
0109 * overwrite marvell,pins on board level if required.
0110 */
0111 pmx_uart0: pmx-uart0 {
0112 marvell,pins = "mpp10", "mpp11";
0113 marvell,function = "uart0";
0114 };
0115
0116 pmx_uart1: pmx-uart1 {
0117 marvell,pins = "mpp13", "mpp14";
0118 marvell,function = "uart1";
0119 };
0120 };
0121
0122 core_clk: core-clocks@10030 {
0123 compatible = "marvell,kirkwood-core-clock";
0124 reg = <0x10030 0x4>;
0125 #clock-cells = <1>;
0126 };
0127
0128 spi0: spi@10600 {
0129 compatible = "marvell,orion-spi";
0130 #address-cells = <1>;
0131 #size-cells = <0>;
0132 cell-index = <0>;
0133 interrupts = <23>;
0134 reg = <0x10600 0x28>;
0135 clocks = <&gate_clk 7>;
0136 pinctrl-0 = <&pmx_spi>;
0137 pinctrl-names = "default";
0138 status = "disabled";
0139 };
0140
0141 gpio0: gpio@10100 {
0142 compatible = "marvell,orion-gpio";
0143 #gpio-cells = <2>;
0144 gpio-controller;
0145 reg = <0x10100 0x40>;
0146 ngpios = <32>;
0147 interrupt-controller;
0148 #interrupt-cells = <2>;
0149 interrupts = <35>, <36>, <37>, <38>;
0150 clocks = <&gate_clk 7>;
0151 };
0152
0153 gpio1: gpio@10140 {
0154 compatible = "marvell,orion-gpio";
0155 #gpio-cells = <2>;
0156 gpio-controller;
0157 reg = <0x10140 0x40>;
0158 ngpios = <18>;
0159 interrupt-controller;
0160 #interrupt-cells = <2>;
0161 interrupts = <39>, <40>, <41>;
0162 clocks = <&gate_clk 7>;
0163 };
0164
0165 i2c0: i2c@11000 {
0166 compatible = "marvell,mv64xxx-i2c";
0167 reg = <0x11000 0x20>;
0168 #address-cells = <1>;
0169 #size-cells = <0>;
0170 interrupts = <29>;
0171 clock-frequency = <100000>;
0172 clocks = <&gate_clk 7>;
0173 pinctrl-0 = <&pmx_twsi0>;
0174 pinctrl-names = "default";
0175 status = "disabled";
0176 };
0177
0178 uart0: serial@12000 {
0179 compatible = "ns16550a";
0180 reg = <0x12000 0x100>;
0181 reg-shift = <2>;
0182 interrupts = <33>;
0183 clocks = <&gate_clk 7>;
0184 pinctrl-0 = <&pmx_uart0>;
0185 pinctrl-names = "default";
0186 status = "disabled";
0187 };
0188
0189 uart1: serial@12100 {
0190 compatible = "ns16550a";
0191 reg = <0x12100 0x100>;
0192 reg-shift = <2>;
0193 interrupts = <34>;
0194 clocks = <&gate_clk 7>;
0195 pinctrl-0 = <&pmx_uart1>;
0196 pinctrl-names = "default";
0197 status = "disabled";
0198 };
0199
0200 mbusc: mbus-controller@20000 {
0201 compatible = "marvell,mbus-controller";
0202 reg = <0x20000 0x80>, <0x1500 0x20>;
0203 };
0204
0205 sysc: system-controller@20000 {
0206 compatible = "marvell,orion-system-controller";
0207 reg = <0x20000 0x120>;
0208 };
0209
0210 bridge_intc: bridge-interrupt-ctrl@20110 {
0211 compatible = "marvell,orion-bridge-intc";
0212 interrupt-controller;
0213 #interrupt-cells = <1>;
0214 reg = <0x20110 0x8>;
0215 interrupts = <1>;
0216 marvell,#interrupts = <6>;
0217 };
0218
0219 gate_clk: clock-gating-control@2011c {
0220 compatible = "marvell,kirkwood-gating-clock";
0221 reg = <0x2011c 0x4>;
0222 clocks = <&core_clk 0>;
0223 #clock-cells = <1>;
0224 };
0225
0226 l2: l2-cache@20128 {
0227 compatible = "marvell,kirkwood-cache";
0228 reg = <0x20128 0x4>;
0229 };
0230
0231 intc: interrupt-controller@20200 {
0232 compatible = "marvell,orion-intc";
0233 interrupt-controller;
0234 #interrupt-cells = <1>;
0235 reg = <0x20200 0x10>, <0x20210 0x10>;
0236 };
0237
0238 timer: timer@20300 {
0239 compatible = "marvell,orion-timer";
0240 reg = <0x20300 0x20>;
0241 interrupt-parent = <&bridge_intc>;
0242 interrupts = <1>, <2>;
0243 clocks = <&core_clk 0>;
0244 };
0245
0246 wdt: watchdog-timer@20300 {
0247 compatible = "marvell,orion-wdt";
0248 reg = <0x20300 0x28>, <0x20108 0x4>;
0249 interrupt-parent = <&bridge_intc>;
0250 interrupts = <3>;
0251 clocks = <&gate_clk 7>;
0252 status = "okay";
0253 };
0254
0255 cesa: crypto@30000 {
0256 compatible = "marvell,kirkwood-crypto";
0257 reg = <0x30000 0x10000>;
0258 reg-names = "regs";
0259 interrupts = <22>;
0260 clocks = <&gate_clk 17>;
0261 marvell,crypto-srams = <&crypto_sram>;
0262 marvell,crypto-sram-size = <0x800>;
0263 status = "okay";
0264 };
0265
0266 usb0: ehci@50000 {
0267 compatible = "marvell,orion-ehci";
0268 reg = <0x50000 0x1000>;
0269 interrupts = <19>;
0270 clocks = <&gate_clk 3>;
0271 status = "okay";
0272 };
0273
0274 dma0: xor@60800 {
0275 compatible = "marvell,orion-xor";
0276 reg = <0x60800 0x100
0277 0x60A00 0x100>;
0278 status = "okay";
0279 clocks = <&gate_clk 8>;
0280
0281 xor00 {
0282 interrupts = <5>;
0283 dmacap,memcpy;
0284 dmacap,xor;
0285 };
0286 xor01 {
0287 interrupts = <6>;
0288 dmacap,memcpy;
0289 dmacap,xor;
0290 dmacap,memset;
0291 };
0292 };
0293
0294 dma1: xor@60900 {
0295 compatible = "marvell,orion-xor";
0296 reg = <0x60900 0x100
0297 0x60B00 0x100>;
0298 status = "okay";
0299 clocks = <&gate_clk 16>;
0300
0301 xor00 {
0302 interrupts = <7>;
0303 dmacap,memcpy;
0304 dmacap,xor;
0305 };
0306 xor01 {
0307 interrupts = <8>;
0308 dmacap,memcpy;
0309 dmacap,xor;
0310 dmacap,memset;
0311 };
0312 };
0313
0314 eth0: ethernet-controller@72000 {
0315 compatible = "marvell,kirkwood-eth";
0316 #address-cells = <1>;
0317 #size-cells = <0>;
0318 reg = <0x72000 0x4000>;
0319 clocks = <&gate_clk 0>;
0320 marvell,tx-checksum-limit = <1600>;
0321 status = "disabled";
0322
0323 eth0port: ethernet0-port@0 {
0324 compatible = "marvell,kirkwood-eth-port";
0325 reg = <0>;
0326 interrupts = <11>;
0327 /* overwrite MAC address in bootloader */
0328 local-mac-address = [00 00 00 00 00 00];
0329 /* set phy-handle property in board file */
0330 };
0331 };
0332
0333 mdio: mdio-bus@72004 {
0334 compatible = "marvell,orion-mdio";
0335 #address-cells = <1>;
0336 #size-cells = <0>;
0337 reg = <0x72004 0x84>;
0338 interrupts = <46>;
0339 clocks = <&gate_clk 0>;
0340 status = "disabled";
0341
0342 /* add phy nodes in board file */
0343 };
0344
0345 eth1: ethernet-controller@76000 {
0346 compatible = "marvell,kirkwood-eth";
0347 #address-cells = <1>;
0348 #size-cells = <0>;
0349 reg = <0x76000 0x4000>;
0350 clocks = <&gate_clk 19>;
0351 marvell,tx-checksum-limit = <1600>;
0352 pinctrl-0 = <&pmx_ge1>;
0353 pinctrl-names = "default";
0354 status = "disabled";
0355
0356 eth1port: ethernet1-port@0 {
0357 compatible = "marvell,kirkwood-eth-port";
0358 reg = <0>;
0359 interrupts = <15>;
0360 /* overwrite MAC address in bootloader */
0361 local-mac-address = [00 00 00 00 00 00];
0362 /* set phy-handle property in board file */
0363 };
0364 };
0365
0366 sata_phy0: sata-phy@82000 {
0367 compatible = "marvell,mvebu-sata-phy";
0368 reg = <0x82000 0x0334>;
0369 clocks = <&gate_clk 14>;
0370 clock-names = "sata";
0371 #phy-cells = <0>;
0372 status = "okay";
0373 };
0374
0375 sata_phy1: sata-phy@84000 {
0376 compatible = "marvell,mvebu-sata-phy";
0377 reg = <0x84000 0x0334>;
0378 clocks = <&gate_clk 15>;
0379 clock-names = "sata";
0380 #phy-cells = <0>;
0381 status = "okay";
0382 };
0383
0384 audio0: audio-controller@a0000 {
0385 compatible = "marvell,kirkwood-audio";
0386 #sound-dai-cells = <0>;
0387 reg = <0xa0000 0x2210>;
0388 interrupts = <24>;
0389 clocks = <&gate_clk 9>;
0390 clock-names = "internal";
0391 status = "disabled";
0392 };
0393 };
0394 };
