0001 // SPDX-License-Identifier: GPL-2.0
0002 / {
0003 mbus@f1000000 {
0004 pciec: pcie@82000000 {
0005 compatible = "marvell,kirkwood-pcie";
0006 status = "disabled";
0007 device_type = "pci";
0008
0009 #address-cells = <3>;
0010 #size-cells = <2>;
0011
0012 bus-range = <0x00 0xff>;
0013
0014 ranges =
0015 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
0016 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0017 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
0018
0019 pcie0: pcie@1,0 {
0020 device_type = "pci";
0021 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
0022 reg = <0x0800 0 0 0 0>;
0023 #address-cells = <3>;
0024 #size-cells = <2>;
0025 #interrupt-cells = <1>;
0026 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0027 0x81000000 0 0 0x81000000 0x1 0 1 0>;
0028 bus-range = <0x00 0xff>;
0029 interrupt-map-mask = <0 0 0 0>;
0030 interrupt-map = <0 0 0 0 &intc 9>;
0031 marvell,pcie-port = <0>;
0032 marvell,pcie-lane = <0>;
0033 clocks = <&gate_clk 2>;
0034 status = "disabled";
0035 };
0036 };
0037 };
0038
0039 ocp@f1000000 {
0040 pinctrl: pin-controller@10000 {
0041 compatible = "marvell,98dx4122-pinctrl";
0042
0043 };
0044 };
0045 };
0046
0047 &sata_phy0 {
0048 status = "disabled";
0049 };
0050
0051 &sata_phy1 {
0052 status = "disabled";
0053 };
