0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Keystone 2 Lamarr SoC specific device tree
0004 *
0005 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
0006 */
0007
0008 #include <dt-bindings/reset/ti-syscon.h>
0009
0010 / {
0011 compatible = "ti,k2l", "ti,keystone";
0012 model = "Texas Instruments Keystone 2 Lamarr SoC";
0013
0014 cpus {
0015 #address-cells = <1>;
0016 #size-cells = <0>;
0017
0018 interrupt-parent = <&gic>;
0019
0020 cpu@0 {
0021 compatible = "arm,cortex-a15";
0022 device_type = "cpu";
0023 reg = <0>;
0024 };
0025
0026 cpu@1 {
0027 compatible = "arm,cortex-a15";
0028 device_type = "cpu";
0029 reg = <1>;
0030 };
0031 };
0032
0033 aliases {
0034 rproc0 = &dsp0;
0035 rproc1 = &dsp1;
0036 rproc2 = &dsp2;
0037 rproc3 = &dsp3;
0038 };
0039 };
0040
0041 &soc0 {
0042 /include/ "keystone-k2l-clocks.dtsi"
0043
0044 uart2: serial@2348400 {
0045 compatible = "ti,da830-uart", "ns16550a";
0046 current-speed = <115200>;
0047 reg-shift = <2>;
0048 reg-io-width = <4>;
0049 reg = <0x02348400 0x100>;
0050 clocks = <&clkuart2>;
0051 interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>;
0052 };
0053
0054 uart3: serial@2348800 {
0055 compatible = "ti,da830-uart", "ns16550a";
0056 current-speed = <115200>;
0057 reg-shift = <2>;
0058 reg-io-width = <4>;
0059 reg = <0x02348800 0x100>;
0060 clocks = <&clkuart3>;
0061 interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
0062 };
0063
0064 gpio1: gpio@2348000 {
0065 compatible = "ti,keystone-gpio";
0066 reg = <0x02348000 0x100>;
0067 gpio-controller;
0068 #gpio-cells = <2>;
0069 /* HW Interrupts mapped to GPIO pins */
0070 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>,
0071 <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
0072 <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>,
0073 <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>,
0074 <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>,
0075 <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
0076 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
0077 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
0078 <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
0079 <GIC_SPI 161 IRQ_TYPE_EDGE_RISING>,
0080 <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
0081 <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
0082 <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>,
0083 <GIC_SPI 165 IRQ_TYPE_EDGE_RISING>,
0084 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
0085 <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
0086 <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>,
0087 <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>,
0088 <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
0089 <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
0090 <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
0091 <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
0092 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
0093 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
0094 <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
0095 <GIC_SPI 401 IRQ_TYPE_EDGE_RISING>,
0096 <GIC_SPI 402 IRQ_TYPE_EDGE_RISING>,
0097 <GIC_SPI 403 IRQ_TYPE_EDGE_RISING>,
0098 <GIC_SPI 404 IRQ_TYPE_EDGE_RISING>,
0099 <GIC_SPI 405 IRQ_TYPE_EDGE_RISING>,
0100 <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
0101 <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>;
0102 clocks = <&clkgpio>;
0103 clock-names = "gpio";
0104 ti,ngpio = <32>;
0105 ti,davinci-gpio-unbanked = <32>;
0106 };
0107
0108 k2l_pmx: pinmux@2620690 {
0109 compatible = "pinctrl-single";
0110 reg = <0x02620690 0xc>;
0111 #address-cells = <1>;
0112 #size-cells = <0>;
0113 #pinctrl-cells = <2>;
0114 pinctrl-single,bit-per-mux;
0115 pinctrl-single,register-width = <32>;
0116 pinctrl-single,function-mask = <0x1>;
0117 status = "disabled";
0118
0119 uart3_emifa_pins: pinmux_uart3_emifa_pins {
0120 pinctrl-single,bits = <
0121 /* UART3_EMIFA_SEL */
0122 0x0 0x0 0xc0
0123 >;
0124 };
0125
0126 uart2_emifa_pins: pinmux_uart2_emifa_pins {
0127 pinctrl-single,bits = <
0128 /* UART2_EMIFA_SEL */
0129 0x0 0x0 0x30
0130 >;
0131 };
0132
0133 uart01_spi2_pins: pinmux_uart01_spi2_pins {
0134 pinctrl-single,bits = <
0135 /* UART01_SPI2_SEL */
0136 0x0 0x0 0x4
0137 >;
0138 };
0139
0140 dfesync_rp1_pins: pinmux_dfesync_rp1_pins{
0141 pinctrl-single,bits = <
0142 /* DFESYNC_RP1_SEL */
0143 0x0 0x0 0x2
0144 >;
0145 };
0146
0147 avsif_pins: pinmux_avsif_pins {
0148 pinctrl-single,bits = <
0149 /* AVSIF_SEL */
0150 0x0 0x0 0x1
0151 >;
0152 };
0153
0154 gpio_emu_pins: pinmux_gpio_emu_pins {
0155 pinctrl-single,bits = <
0156 /*
0157 * GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33
0158 * GPIO_EMU_SEL[30]: 0-GPIO30, 1-EMU32
0159 * GPIO_EMU_SEL[29]: 0-GPIO29, 1-EMU31
0160 * GPIO_EMU_SEL[28]: 0-GPIO28, 1-EMU30
0161 * GPIO_EMU_SEL[27]: 0-GPIO27, 1-EMU29
0162 * GPIO_EMU_SEL[26]: 0-GPIO26, 1-EMU28
0163 * GPIO_EMU_SEL[25]: 0-GPIO25, 1-EMU27
0164 * GPIO_EMU_SEL[24]: 0-GPIO24, 1-EMU26
0165 * GPIO_EMU_SEL[23]: 0-GPIO23, 1-EMU25
0166 * GPIO_EMU_SEL[22]: 0-GPIO22, 1-EMU24
0167 * GPIO_EMU_SEL[21]: 0-GPIO21, 1-EMU23
0168 * GPIO_EMU_SEL[20]: 0-GPIO20, 1-EMU22
0169 * GPIO_EMU_SEL[19]: 0-GPIO19, 1-EMU21
0170 * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20
0171 * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19
0172 */
0173 0x4 0x0000 0xFFFE0000
0174 >;
0175 };
0176
0177 gpio_timio_pins: pinmux_gpio_timio_pins {
0178 pinctrl-single,bits = <
0179 /*
0180 * GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7
0181 * GPIO_TIMIO_SEL[14]: 0-GPIO14, 1-TIMO6
0182 * GPIO_TIMIO_SEL[13]: 0-GPIO13, 1-TIMO5
0183 * GPIO_TIMIO_SEL[12]: 0-GPIO12, 1-TIMO4
0184 * GPIO_TIMIO_SEL[11]: 0-GPIO11, 1-TIMO3
0185 * GPIO_TIMIO_SEL[10]: 0-GPIO10, 1-TIMO2
0186 * GPIO_TIMIO_SEL[9]: 0-GPIO9, 1-TIMI7
0187 * GPIO_TIMIO_SEL[8]: 0-GPIO8, 1-TIMI6
0188 * GPIO_TIMIO_SEL[7]: 0-GPIO7, 1-TIMI5
0189 * GPIO_TIMIO_SEL[6]: 0-GPIO6, 1-TIMI4
0190 * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3
0191 * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2
0192 */
0193 0x4 0x0 0xFFF0
0194 >;
0195 };
0196
0197 gpio_spi2cs_pins: pinmux_gpio_spi2cs_pins {
0198 pinctrl-single,bits = <
0199 /*
0200 * GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4
0201 * GPIO_SPI2CS_SEL[2]: 0-GPIO2, 1-SPI2CS3
0202 * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2
0203 * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1
0204 */
0205 0x4 0x0 0xF
0206 >;
0207 };
0208
0209 gpio_dfeio_pins: pinmux_gpio_dfeio_pins {
0210 pinctrl-single,bits = <
0211 /*
0212 * GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63
0213 * GPIO_DFEIO_SEL[30]: 0-DFEIO16, 1-GPIO62
0214 * GPIO_DFEIO_SEL[29]: 0-DFEIO15, 1-GPIO61
0215 * GPIO_DFEIO_SEL[28]: 0-DFEIO14, 1-GPIO60
0216 * GPIO_DFEIO_SEL[27]: 0-DFEIO13, 1-GPIO59
0217 * GPIO_DFEIO_SEL[26]: 0-DFEIO12, 1-GPIO58
0218 * GPIO_DFEIO_SEL[25]: 0-DFEIO11, 1-GPIO57
0219 * GPIO_DFEIO_SEL[24]: 0-DFEIO10, 1-GPIO56
0220 * GPIO_DFEIO_SEL[23]: 0-DFEIO9, 1-GPIO55
0221 * GPIO_DFEIO_SEL[22]: 0-DFEIO8, 1-GPIO54
0222 * GPIO_DFEIO_SEL[21]: 0-DFEIO7, 1-GPIO53
0223 * GPIO_DFEIO_SEL[20]: 0-DFEIO6, 1-GPIO52
0224 * GPIO_DFEIO_SEL[19]: 0-DFEIO5, 1-GPIO51
0225 * GPIO_DFEIO_SEL[18]: 0-DFEIO4, 1-GPIO50
0226 * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49
0227 * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48
0228 */
0229 0x8 0x0 0xFFFF0000
0230 >;
0231 };
0232
0233 gpio_emifa_pins: pinmux_gpio_emifa_pins {
0234 pinctrl-single,bits = <
0235 /*
0236 * GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47
0237 * GPIO_EMIFA_SEL[14]: 0-EMIFA16, 1-GPIO46
0238 * GPIO_EMIFA_SEL[13]: 0-EMIFA15, 1-GPIO45
0239 * GPIO_EMIFA_SEL[12]: 0-EMIFA14, 1-GPIO44
0240 * GPIO_EMIFA_SEL[11]: 0-EMIFA13, 1-GPIO43
0241 * GPIO_EMIFA_SEL[10]: 0-EMIFA10, 1-GPIO42
0242 * GPIO_EMIFA_SEL[9]: 0-EMIFA9, 1-GPIO41
0243 * GPIO_EMIFA_SEL[8]: 0-EMIFA8, 1-GPIO40
0244 * GPIO_EMIFA_SEL[7]: 0-EMIFA7, 1-GPIO39
0245 * GPIO_EMIFA_SEL[6]: 0-EMIFA6, 1-GPIO38
0246 * GPIO_EMIFA_SEL[5]: 0-EMIFA5, 1-GPIO37
0247 * GPIO_EMIFA_SEL[4]: 0-EMIFA4, 1-GPIO36
0248 * GPIO_EMIFA_SEL[3]: 0-EMIFA3, 1-GPIO35
0249 * GPIO_EMIFA_SEL[2]: 0-EMIFA2, 1-GPIO34
0250 * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33
0251 * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32
0252 */
0253 0x8 0x0 0xFFFF
0254 >;
0255 };
0256 };
0257
0258 msm_ram: sram@c000000 {
0259 compatible = "mmio-sram";
0260 reg = <0x0c000000 0x200000>;
0261 ranges = <0x0 0x0c000000 0x200000>;
0262 #address-cells = <1>;
0263 #size-cells = <1>;
0264
0265 bm-sram@1f8000 {
0266 reg = <0x001f8000 0x8000>;
0267 };
0268 };
0269
0270 psc: power-sleep-controller@2350000 {
0271 pscrst: reset-controller {
0272 compatible = "ti,k2l-pscrst", "ti,syscon-reset";
0273 #reset-cells = <1>;
0274
0275 ti,reset-bits = <
0276 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
0277 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */
0278 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */
0279 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */
0280 >;
0281 };
0282 };
0283
0284 osr: sram@70000000 {
0285 compatible = "mmio-sram";
0286 reg = <0x70000000 0x10000>;
0287 #address-cells = <1>;
0288 #size-cells = <1>;
0289 clocks = <&clkosr>;
0290 };
0291
0292 devctrl: device-state-control@2620000 {
0293 dspgpio0: keystone_dsp_gpio@240 {
0294 compatible = "ti,keystone-dsp-gpio";
0295 reg = <0x240 0x4>;
0296 gpio-controller;
0297 #gpio-cells = <2>;
0298 gpio,syscon-dev = <&devctrl 0x240>;
0299 };
0300
0301 dspgpio1: keystone_dsp_gpio@244 {
0302 compatible = "ti,keystone-dsp-gpio";
0303 reg = <0x244 0x4>;
0304 gpio-controller;
0305 #gpio-cells = <2>;
0306 gpio,syscon-dev = <&devctrl 0x244>;
0307 };
0308
0309 dspgpio2: keystone_dsp_gpio@248 {
0310 compatible = "ti,keystone-dsp-gpio";
0311 reg = <0x248 0x4>;
0312 gpio-controller;
0313 #gpio-cells = <2>;
0314 gpio,syscon-dev = <&devctrl 0x248>;
0315 };
0316
0317 dspgpio3: keystone_dsp_gpio@24c {
0318 compatible = "ti,keystone-dsp-gpio";
0319 reg = <0x24c 0x4>;
0320 gpio-controller;
0321 #gpio-cells = <2>;
0322 gpio,syscon-dev = <&devctrl 0x24c>;
0323 };
0324 };
0325
0326 dsp0: dsp@10800000 {
0327 compatible = "ti,k2l-dsp";
0328 reg = <0x10800000 0x00100000>,
0329 <0x10e00000 0x00008000>,
0330 <0x10f00000 0x00008000>;
0331 reg-names = "l2sram", "l1pram", "l1dram";
0332 clocks = <&clkgem0>;
0333 ti,syscon-dev = <&devctrl 0x844>;
0334 resets = <&pscrst 0>;
0335 interrupt-parent = <&kirq0>;
0336 interrupts = <0 8>;
0337 interrupt-names = "vring", "exception";
0338 kick-gpios = <&dspgpio0 27 0>;
0339 status = "disabled";
0340 };
0341
0342 dsp1: dsp@11800000 {
0343 compatible = "ti,k2l-dsp";
0344 reg = <0x11800000 0x00100000>,
0345 <0x11e00000 0x00008000>,
0346 <0x11f00000 0x00008000>;
0347 reg-names = "l2sram", "l1pram", "l1dram";
0348 clocks = <&clkgem1>;
0349 ti,syscon-dev = <&devctrl 0x848>;
0350 resets = <&pscrst 1>;
0351 interrupt-parent = <&kirq0>;
0352 interrupts = <1 9>;
0353 interrupt-names = "vring", "exception";
0354 kick-gpios = <&dspgpio1 27 0>;
0355 status = "disabled";
0356 };
0357
0358 dsp2: dsp@12800000 {
0359 compatible = "ti,k2l-dsp";
0360 reg = <0x12800000 0x00100000>,
0361 <0x12e00000 0x00008000>,
0362 <0x12f00000 0x00008000>;
0363 reg-names = "l2sram", "l1pram", "l1dram";
0364 clocks = <&clkgem2>;
0365 ti,syscon-dev = <&devctrl 0x84c>;
0366 resets = <&pscrst 2>;
0367 interrupt-parent = <&kirq0>;
0368 interrupts = <2 10>;
0369 interrupt-names = "vring", "exception";
0370 kick-gpios = <&dspgpio2 27 0>;
0371 status = "disabled";
0372 };
0373
0374 dsp3: dsp@13800000 {
0375 compatible = "ti,k2l-dsp";
0376 reg = <0x13800000 0x00100000>,
0377 <0x13e00000 0x00008000>,
0378 <0x13f00000 0x00008000>;
0379 reg-names = "l2sram", "l1pram", "l1dram";
0380 clocks = <&clkgem3>;
0381 ti,syscon-dev = <&devctrl 0x850>;
0382 resets = <&pscrst 3>;
0383 interrupt-parent = <&kirq0>;
0384 interrupts = <3 11>;
0385 interrupt-names = "vring", "exception";
0386 kick-gpios = <&dspgpio3 27 0>;
0387 status = "disabled";
0388 };
0389
0390 mdio: mdio@26200f00 {
0391 compatible = "ti,keystone_mdio", "ti,davinci_mdio";
0392 #address-cells = <1>;
0393 #size-cells = <0>;
0394 reg = <0x26200f00 0x100>;
0395 status = "disabled";
0396 clocks = <&clkcpgmac>;
0397 clock-names = "fck";
0398 bus_freq = <2500000>;
0399 };
0400 /include/ "keystone-k2l-netcp.dtsi"
0401 };
0402
0403 &spi0 {
0404 ti,davinci-spi-num-cs = <5>;
0405 };
0406
0407 &spi1 {
0408 ti,davinci-spi-num-cs = <3>;
0409 };
0410
0411 &spi2 {
0412 ti,davinci-spi-num-cs = <5>;
0413 /* Pin muxed. Enabled and configured by Bootloader */
0414 status = "disabled";
0415 };
