0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Keystone 2 lamarr SoC clock nodes
0004 *
0005 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
0006 */
0007
0008 clocks {
0009 armpllclk: armpllclk@2620370 {
0010 #clock-cells = <0>;
0011 compatible = "ti,keystone,pll-clock";
0012 clocks = <&refclksys>;
0013 clock-output-names = "arm-pll-clk";
0014 reg = <0x02620370 4>;
0015 reg-names = "control";
0016 };
0017
0018 mainpllclk: mainpllclk@2310110 {
0019 #clock-cells = <0>;
0020 compatible = "ti,keystone,main-pll-clock";
0021 clocks = <&refclksys>;
0022 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
0023 reg-names = "control", "multiplier", "post-divider";
0024 };
0025
0026 papllclk: papllclk@2620358 {
0027 #clock-cells = <0>;
0028 compatible = "ti,keystone,pll-clock";
0029 clocks = <&refclksys>;
0030 clock-output-names = "papllclk";
0031 reg = <0x02620358 4>;
0032 reg-names = "control";
0033 };
0034
0035 ddr3apllclk: ddr3apllclk@2620360 {
0036 #clock-cells = <0>;
0037 compatible = "ti,keystone,pll-clock";
0038 clocks = <&refclksys>;
0039 clock-output-names = "ddr-3a-pll-clk";
0040 reg = <0x02620360 4>;
0041 reg-names = "control";
0042 };
0043
0044 clkdfeiqnsys: clkdfeiqnsys@2350004 {
0045 #clock-cells = <0>;
0046 compatible = "ti,keystone,psc-clock";
0047 clocks = <&chipclk12>;
0048 clock-output-names = "dfe";
0049 reg-names = "control", "domain";
0050 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
0051 domain-id = <0>;
0052 };
0053
0054 clkpcie1: clkpcie1@235002c {
0055 #clock-cells = <0>;
0056 compatible = "ti,keystone,psc-clock";
0057 clocks = <&chipclk12>;
0058 clock-output-names = "pcie";
0059 reg = <0x0235002c 0xb00>, <0x02350000 0x400>;
0060 reg-names = "control", "domain";
0061 domain-id = <4>;
0062 };
0063
0064 clkgem1: clkgem1@2350040 {
0065 #clock-cells = <0>;
0066 compatible = "ti,keystone,psc-clock";
0067 clocks = <&chipclk1>;
0068 clock-output-names = "gem1";
0069 reg = <0x02350040 0xb00>, <0x02350024 0x400>;
0070 reg-names = "control", "domain";
0071 domain-id = <9>;
0072 };
0073
0074 clkgem2: clkgem2@2350044 {
0075 #clock-cells = <0>;
0076 compatible = "ti,keystone,psc-clock";
0077 clocks = <&chipclk1>;
0078 clock-output-names = "gem2";
0079 reg = <0x02350044 0xb00>, <0x02350028 0x400>;
0080 reg-names = "control", "domain";
0081 domain-id = <10>;
0082 };
0083
0084 clkgem3: clkgem3@2350048 {
0085 #clock-cells = <0>;
0086 compatible = "ti,keystone,psc-clock";
0087 clocks = <&chipclk1>;
0088 clock-output-names = "gem3";
0089 reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
0090 reg-names = "control", "domain";
0091 domain-id = <11>;
0092 };
0093
0094 clktac: clktac@2350064 {
0095 #clock-cells = <0>;
0096 compatible = "ti,keystone,psc-clock";
0097 clocks = <&chipclk13>;
0098 clock-output-names = "tac";
0099 reg = <0x02350064 0xb00>, <0x02350044 0x400>;
0100 reg-names = "control", "domain";
0101 domain-id = <17>;
0102 };
0103
0104 clkrac: clkrac@2350068 {
0105 #clock-cells = <0>;
0106 compatible = "ti,keystone,psc-clock";
0107 clocks = <&chipclk13>;
0108 clock-output-names = "rac";
0109 reg = <0x02350068 0xb00>, <0x02350044 0x400>;
0110 reg-names = "control", "domain";
0111 domain-id = <17>;
0112 };
0113
0114 clkdfepd0: clkdfepd0@235006c {
0115 #clock-cells = <0>;
0116 compatible = "ti,keystone,psc-clock";
0117 clocks = <&chipclk13>;
0118 clock-output-names = "dfe-pd0";
0119 reg = <0x0235006c 0xb00>, <0x02350044 0x400>;
0120 reg-names = "control", "domain";
0121 domain-id = <18>;
0122 };
0123
0124 clkfftc0: clkfftc0@2350070 {
0125 #clock-cells = <0>;
0126 compatible = "ti,keystone,psc-clock";
0127 clocks = <&chipclk13>;
0128 clock-output-names = "fftc-0";
0129 reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
0130 reg-names = "control", "domain";
0131 domain-id = <19>;
0132 };
0133
0134 clkosr: clkosr@2350088 {
0135 #clock-cells = <0>;
0136 compatible = "ti,keystone,psc-clock";
0137 clocks = <&chipclk13>;
0138 clock-output-names = "osr";
0139 reg = <0x02350088 0xb00>, <0x0235004c 0x400>;
0140 reg-names = "control", "domain";
0141 domain-id = <21>;
0142 };
0143
0144 clktcp3d0: clktcp3d0@235008c {
0145 #clock-cells = <0>;
0146 compatible = "ti,keystone,psc-clock";
0147 clocks = <&chipclk13>;
0148 clock-output-names = "tcp3d-0";
0149 reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
0150 reg-names = "control", "domain";
0151 domain-id = <22>;
0152 };
0153
0154 clktcp3d1: clktcp3d1@2350094 {
0155 #clock-cells = <0>;
0156 compatible = "ti,keystone,psc-clock";
0157 clocks = <&chipclk13>;
0158 clock-output-names = "tcp3d-1";
0159 reg = <0x02350094 0xb00>, <0x02350058 0x400>;
0160 reg-names = "control", "domain";
0161 domain-id = <23>;
0162 };
0163
0164 clkvcp0: clkvcp0@235009c {
0165 #clock-cells = <0>;
0166 compatible = "ti,keystone,psc-clock";
0167 clocks = <&chipclk13>;
0168 clock-output-names = "vcp-0";
0169 reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
0170 reg-names = "control", "domain";
0171 domain-id = <24>;
0172 };
0173
0174 clkvcp1: clkvcp1@23500a0 {
0175 #clock-cells = <0>;
0176 compatible = "ti,keystone,psc-clock";
0177 clocks = <&chipclk13>;
0178 clock-output-names = "vcp-1";
0179 reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
0180 reg-names = "control", "domain";
0181 domain-id = <24>;
0182 };
0183
0184 clkvcp2: clkvcp2@23500a4 {
0185 #clock-cells = <0>;
0186 compatible = "ti,keystone,psc-clock";
0187 clocks = <&chipclk13>;
0188 clock-output-names = "vcp-2";
0189 reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
0190 reg-names = "control", "domain";
0191 domain-id = <24>;
0192 };
0193
0194 clkvcp3: clkvcp3@23500a8 {
0195 #clock-cells = <0>;
0196 compatible = "ti,keystone,psc-clock";
0197 clocks = <&chipclk13>;
0198 clock-output-names = "vcp-3";
0199 reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
0200 reg-names = "control", "domain";
0201 domain-id = <24>;
0202 };
0203
0204 clkbcp: clkbcp@23500bc {
0205 #clock-cells = <0>;
0206 compatible = "ti,keystone,psc-clock";
0207 clocks = <&chipclk13>;
0208 clock-output-names = "bcp";
0209 reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
0210 reg-names = "control", "domain";
0211 domain-id = <26>;
0212 };
0213
0214 clkdfepd1: clkdfepd1@23500c0 {
0215 #clock-cells = <0>;
0216 compatible = "ti,keystone,psc-clock";
0217 clocks = <&chipclk13>;
0218 clock-output-names = "dfe-pd1";
0219 reg = <0x023500c0 0xb00>, <0x02350044 0x400>;
0220 reg-names = "control", "domain";
0221 domain-id = <27>;
0222 };
0223
0224 clkfftc1: clkfftc1@23500c4 {
0225 #clock-cells = <0>;
0226 compatible = "ti,keystone,psc-clock";
0227 clocks = <&chipclk13>;
0228 clock-output-names = "fftc-1";
0229 reg = <0x023500c4 0xb00>, <0x023504c0 0x400>;
0230 reg-names = "control", "domain";
0231 domain-id = <28>;
0232 };
0233
0234 clkiqnail: clkiqnail@23500c8 {
0235 #clock-cells = <0>;
0236 compatible = "ti,keystone,psc-clock";
0237 clocks = <&chipclk13>;
0238 clock-output-names = "iqn-ail";
0239 reg = <0x023500c8 0xb00>, <0x0235004c 0x400>;
0240 reg-names = "control", "domain";
0241 domain-id = <29>;
0242 };
0243
0244 clkuart2: clkuart2@2350000 {
0245 #clock-cells = <0>;
0246 compatible = "ti,keystone,psc-clock";
0247 clocks = <&clkmodrst0>;
0248 clock-output-names = "uart2";
0249 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
0250 reg-names = "control", "domain";
0251 domain-id = <0>;
0252 };
0253
0254 clkuart3: clkuart3@2350000 {
0255 #clock-cells = <0>;
0256 compatible = "ti,keystone,psc-clock";
0257 clocks = <&clkmodrst0>;
0258 clock-output-names = "uart3";
0259 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
0260 reg-names = "control", "domain";
0261 domain-id = <0>;
0262 };
0263 };
