0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Keystone 2 Kepler/Hawking SoC clock nodes
0004 *
0005 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
0006 */
0007
0008 clocks {
0009 armpllclk: armpllclk@2620370 {
0010 #clock-cells = <0>;
0011 compatible = "ti,keystone,pll-clock";
0012 clocks = <&refclkarm>;
0013 clock-output-names = "arm-pll-clk";
0014 reg = <0x02620370 4>;
0015 reg-names = "control";
0016 };
0017
0018 mainpllclk: mainpllclk@2310110 {
0019 #clock-cells = <0>;
0020 compatible = "ti,keystone,main-pll-clock";
0021 clocks = <&refclksys>;
0022 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
0023 reg-names = "control", "multiplier", "post-divider";
0024 };
0025
0026 papllclk: papllclk@2620358 {
0027 #clock-cells = <0>;
0028 compatible = "ti,keystone,pll-clock";
0029 clocks = <&refclkpass>;
0030 clock-output-names = "papllclk";
0031 reg = <0x02620358 4>;
0032 reg-names = "control";
0033 };
0034
0035 ddr3apllclk: ddr3apllclk@2620360 {
0036 #clock-cells = <0>;
0037 compatible = "ti,keystone,pll-clock";
0038 clocks = <&refclkddr3a>;
0039 clock-output-names = "ddr-3a-pll-clk";
0040 reg = <0x02620360 4>;
0041 reg-names = "control";
0042 };
0043
0044 ddr3bpllclk: ddr3bpllclk@2620368 {
0045 #clock-cells = <0>;
0046 compatible = "ti,keystone,pll-clock";
0047 clocks = <&refclkddr3b>;
0048 clock-output-names = "ddr-3b-pll-clk";
0049 reg = <0x02620368 4>;
0050 reg-names = "control";
0051 };
0052
0053 clktsip: clktsip@2350000 {
0054 #clock-cells = <0>;
0055 compatible = "ti,keystone,psc-clock";
0056 clocks = <&chipclk16>;
0057 clock-output-names = "tsip";
0058 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
0059 reg-names = "control", "domain";
0060 domain-id = <0>;
0061 };
0062
0063 clksrio: clksrio@235002c {
0064 #clock-cells = <0>;
0065 compatible = "ti,keystone,psc-clock";
0066 clocks = <&chipclk1rstiso13>;
0067 clock-output-names = "srio";
0068 reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
0069 reg-names = "control", "domain";
0070 domain-id = <4>;
0071 };
0072
0073 clkhyperlink0: clkhyperlink0@2350030 {
0074 #clock-cells = <0>;
0075 compatible = "ti,keystone,psc-clock";
0076 clocks = <&chipclk12>;
0077 clock-output-names = "hyperlink-0";
0078 reg = <0x02350030 0xb00>, <0x02350014 0x400>;
0079 reg-names = "control", "domain";
0080 domain-id = <5>;
0081 };
0082
0083 clkgem1: clkgem1@2350040 {
0084 #clock-cells = <0>;
0085 compatible = "ti,keystone,psc-clock";
0086 clocks = <&chipclk1>;
0087 clock-output-names = "gem1";
0088 reg = <0x02350040 0xb00>, <0x02350024 0x400>;
0089 reg-names = "control", "domain";
0090 domain-id = <9>;
0091 };
0092
0093 clkgem2: clkgem2@2350044 {
0094 #clock-cells = <0>;
0095 compatible = "ti,keystone,psc-clock";
0096 clocks = <&chipclk1>;
0097 clock-output-names = "gem2";
0098 reg = <0x02350044 0xb00>, <0x02350028 0x400>;
0099 reg-names = "control", "domain";
0100 domain-id = <10>;
0101 };
0102
0103 clkgem3: clkgem3@2350048 {
0104 #clock-cells = <0>;
0105 compatible = "ti,keystone,psc-clock";
0106 clocks = <&chipclk1>;
0107 clock-output-names = "gem3";
0108 reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
0109 reg-names = "control", "domain";
0110 domain-id = <11>;
0111 };
0112
0113 clkgem4: clkgem4@235004c {
0114 #clock-cells = <0>;
0115 compatible = "ti,keystone,psc-clock";
0116 clocks = <&chipclk1>;
0117 clock-output-names = "gem4";
0118 reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
0119 reg-names = "control", "domain";
0120 domain-id = <12>;
0121 };
0122
0123 clkgem5: clkgem5@2350050 {
0124 #clock-cells = <0>;
0125 compatible = "ti,keystone,psc-clock";
0126 clocks = <&chipclk1>;
0127 clock-output-names = "gem5";
0128 reg = <0x02350050 0xb00>, <0x02350034 0x400>;
0129 reg-names = "control", "domain";
0130 domain-id = <13>;
0131 };
0132
0133 clkgem6: clkgem6@2350054 {
0134 #clock-cells = <0>;
0135 compatible = "ti,keystone,psc-clock";
0136 clocks = <&chipclk1>;
0137 clock-output-names = "gem6";
0138 reg = <0x02350054 0xb00>, <0x02350038 0x400>;
0139 reg-names = "control", "domain";
0140 domain-id = <14>;
0141 };
0142
0143 clkgem7: clkgem7@2350058 {
0144 #clock-cells = <0>;
0145 compatible = "ti,keystone,psc-clock";
0146 clocks = <&chipclk1>;
0147 clock-output-names = "gem7";
0148 reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
0149 reg-names = "control", "domain";
0150 domain-id = <15>;
0151 };
0152
0153 clkddr31: clkddr31@2350060 {
0154 #clock-cells = <0>;
0155 compatible = "ti,keystone,psc-clock";
0156 clocks = <&chipclk13>;
0157 clock-output-names = "ddr3-1";
0158 reg = <0x02350060 0xb00>, <0x02350040 0x400>;
0159 reg-names = "control", "domain";
0160 domain-id = <16>;
0161 };
0162
0163 clktac: clktac@2350064 {
0164 #clock-cells = <0>;
0165 compatible = "ti,keystone,psc-clock";
0166 clocks = <&chipclk13>;
0167 clock-output-names = "tac";
0168 reg = <0x02350064 0xb00>, <0x02350044 0x400>;
0169 reg-names = "control", "domain";
0170 domain-id = <17>;
0171 };
0172
0173 clkrac01: clkrac01@2350068 {
0174 #clock-cells = <0>;
0175 compatible = "ti,keystone,psc-clock";
0176 clocks = <&chipclk13>;
0177 clock-output-names = "rac-01";
0178 reg = <0x02350068 0xb00>, <0x02350044 0x400>;
0179 reg-names = "control", "domain";
0180 domain-id = <17>;
0181 };
0182
0183 clkrac23: clkrac23@235006c {
0184 #clock-cells = <0>;
0185 compatible = "ti,keystone,psc-clock";
0186 clocks = <&chipclk13>;
0187 clock-output-names = "rac-23";
0188 reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
0189 reg-names = "control", "domain";
0190 domain-id = <18>;
0191 };
0192
0193 clkfftc0: clkfftc0@2350070 {
0194 #clock-cells = <0>;
0195 compatible = "ti,keystone,psc-clock";
0196 clocks = <&chipclk13>;
0197 clock-output-names = "fftc-0";
0198 reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
0199 reg-names = "control", "domain";
0200 domain-id = <19>;
0201 };
0202
0203 clkfftc1: clkfftc1@2350074 {
0204 #clock-cells = <0>;
0205 compatible = "ti,keystone,psc-clock";
0206 clocks = <&chipclk13>;
0207 clock-output-names = "fftc-1";
0208 reg = <0x02350074 0xb00>, <0x0235004c 0x400>;
0209 reg-names = "control", "domain";
0210 domain-id = <19>;
0211 };
0212
0213 clkfftc2: clkfftc2@2350078 {
0214 #clock-cells = <0>;
0215 compatible = "ti,keystone,psc-clock";
0216 clocks = <&chipclk13>;
0217 clock-output-names = "fftc-2";
0218 reg = <0x02350078 0xb00>, <0x02350050 0x400>;
0219 reg-names = "control", "domain";
0220 domain-id = <20>;
0221 };
0222
0223 clkfftc3: clkfftc3@235007c {
0224 #clock-cells = <0>;
0225 compatible = "ti,keystone,psc-clock";
0226 clocks = <&chipclk13>;
0227 clock-output-names = "fftc-3";
0228 reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
0229 reg-names = "control", "domain";
0230 domain-id = <20>;
0231 };
0232
0233 clkfftc4: clkfftc4@2350080 {
0234 #clock-cells = <0>;
0235 compatible = "ti,keystone,psc-clock";
0236 clocks = <&chipclk13>;
0237 clock-output-names = "fftc-4";
0238 reg = <0x02350080 0xb00>, <0x02350050 0x400>;
0239 reg-names = "control", "domain";
0240 domain-id = <20>;
0241 };
0242
0243 clkfftc5: clkfftc5@2350084 {
0244 #clock-cells = <0>;
0245 compatible = "ti,keystone,psc-clock";
0246 clocks = <&chipclk13>;
0247 clock-output-names = "fftc-5";
0248 reg = <0x02350084 0xb00>, <0x02350050 0x400>;
0249 reg-names = "control", "domain";
0250 domain-id = <20>;
0251 };
0252
0253 clkaif: clkaif@2350088 {
0254 #clock-cells = <0>;
0255 compatible = "ti,keystone,psc-clock";
0256 clocks = <&chipclk13>;
0257 clock-output-names = "aif";
0258 reg = <0x02350088 0xb00>, <0x02350054 0x400>;
0259 reg-names = "control", "domain";
0260 domain-id = <21>;
0261 };
0262
0263 clktcp3d0: clktcp3d0@235008c {
0264 #clock-cells = <0>;
0265 compatible = "ti,keystone,psc-clock";
0266 clocks = <&chipclk13>;
0267 clock-output-names = "tcp3d-0";
0268 reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
0269 reg-names = "control", "domain";
0270 domain-id = <22>;
0271 };
0272
0273 clktcp3d1: clktcp3d1@2350090 {
0274 #clock-cells = <0>;
0275 compatible = "ti,keystone,psc-clock";
0276 clocks = <&chipclk13>;
0277 clock-output-names = "tcp3d-1";
0278 reg = <0x02350090 0xb00>, <0x02350058 0x400>;
0279 reg-names = "control", "domain";
0280 domain-id = <22>;
0281 };
0282
0283 clktcp3d2: clktcp3d2@2350094 {
0284 #clock-cells = <0>;
0285 compatible = "ti,keystone,psc-clock";
0286 clocks = <&chipclk13>;
0287 clock-output-names = "tcp3d-2";
0288 reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
0289 reg-names = "control", "domain";
0290 domain-id = <23>;
0291 };
0292
0293 clktcp3d3: clktcp3d3@2350098 {
0294 #clock-cells = <0>;
0295 compatible = "ti,keystone,psc-clock";
0296 clocks = <&chipclk13>;
0297 clock-output-names = "tcp3d-3";
0298 reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
0299 reg-names = "control", "domain";
0300 domain-id = <23>;
0301 };
0302
0303 clkvcp0: clkvcp0@235009c {
0304 #clock-cells = <0>;
0305 compatible = "ti,keystone,psc-clock";
0306 clocks = <&chipclk13>;
0307 clock-output-names = "vcp-0";
0308 reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
0309 reg-names = "control", "domain";
0310 domain-id = <24>;
0311 };
0312
0313 clkvcp1: clkvcp1@23500a0 {
0314 #clock-cells = <0>;
0315 compatible = "ti,keystone,psc-clock";
0316 clocks = <&chipclk13>;
0317 clock-output-names = "vcp-1";
0318 reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
0319 reg-names = "control", "domain";
0320 domain-id = <24>;
0321 };
0322
0323 clkvcp2: clkvcp2@23500a4 {
0324 #clock-cells = <0>;
0325 compatible = "ti,keystone,psc-clock";
0326 clocks = <&chipclk13>;
0327 clock-output-names = "vcp-2";
0328 reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
0329 reg-names = "control", "domain";
0330 domain-id = <24>;
0331 };
0332
0333 clkvcp3: clkvcp3@23500a8 {
0334 #clock-cells = <0>;
0335 compatible = "ti,keystone,psc-clock";
0336 clocks = <&chipclk13>;
0337 clock-output-names = "vcp-3";
0338 reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
0339 reg-names = "control", "domain";
0340 domain-id = <24>;
0341 };
0342
0343 clkvcp4: clkvcp4@23500ac {
0344 #clock-cells = <0>;
0345 compatible = "ti,keystone,psc-clock";
0346 clocks = <&chipclk13>;
0347 clock-output-names = "vcp-4";
0348 reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
0349 reg-names = "control", "domain";
0350 domain-id = <25>;
0351 };
0352
0353 clkvcp5: clkvcp5@23500b0 {
0354 #clock-cells = <0>;
0355 compatible = "ti,keystone,psc-clock";
0356 clocks = <&chipclk13>;
0357 clock-output-names = "vcp-5";
0358 reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
0359 reg-names = "control", "domain";
0360 domain-id = <25>;
0361 };
0362
0363 clkvcp6: clkvcp6@23500b4 {
0364 #clock-cells = <0>;
0365 compatible = "ti,keystone,psc-clock";
0366 clocks = <&chipclk13>;
0367 clock-output-names = "vcp-6";
0368 reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
0369 reg-names = "control", "domain";
0370 domain-id = <25>;
0371 };
0372
0373 clkvcp7: clkvcp7@23500b8 {
0374 #clock-cells = <0>;
0375 compatible = "ti,keystone,psc-clock";
0376 clocks = <&chipclk13>;
0377 clock-output-names = "vcp-7";
0378 reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
0379 reg-names = "control", "domain";
0380 domain-id = <25>;
0381 };
0382
0383 clkbcp: clkbcp@23500bc {
0384 #clock-cells = <0>;
0385 compatible = "ti,keystone,psc-clock";
0386 clocks = <&chipclk13>;
0387 clock-output-names = "bcp";
0388 reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
0389 reg-names = "control", "domain";
0390 domain-id = <26>;
0391 };
0392
0393 clkdxb: clkdxb@23500c0 {
0394 #clock-cells = <0>;
0395 compatible = "ti,keystone,psc-clock";
0396 clocks = <&chipclk13>;
0397 clock-output-names = "dxb";
0398 reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
0399 reg-names = "control", "domain";
0400 domain-id = <27>;
0401 };
0402
0403 clkhyperlink1: clkhyperlink1@23500c4 {
0404 #clock-cells = <0>;
0405 compatible = "ti,keystone,psc-clock";
0406 clocks = <&chipclk12>;
0407 clock-output-names = "hyperlink-1";
0408 reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
0409 reg-names = "control", "domain";
0410 domain-id = <28>;
0411 };
0412
0413 clkxge: clkxge@23500c8 {
0414 #clock-cells = <0>;
0415 compatible = "ti,keystone,psc-clock";
0416 clocks = <&chipclk13>;
0417 clock-output-names = "xge";
0418 reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
0419 reg-names = "control", "domain";
0420 domain-id = <29>;
0421 };
0422 };
