0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for K2G Industrial Communication Engine EVM
0004 *
0005 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
0006 */
0007 /dts-v1/;
0008
0009 #include "keystone-k2g.dtsi"
0010 #include <dt-bindings/net/ti-dp83867.h>
0011
0012 / {
0013 compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
0014 model = "Texas Instruments K2G Industrial Communication EVM";
0015
0016 memory@800000000 {
0017 device_type = "memory";
0018 reg = <0x00000008 0x00000000 0x00000000 0x20000000>;
0019 };
0020
0021 reserved-memory {
0022 #address-cells = <2>;
0023 #size-cells = <2>;
0024 ranges;
0025
0026 dsp_common_memory: dsp-common-memory@81f800000 {
0027 compatible = "shared-dma-pool";
0028 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
0029 reusable;
0030 status = "okay";
0031 };
0032 };
0033
0034 vmain: fixedregulator-vmain {
0035 compatible = "regulator-fixed";
0036 regulator-name = "vmain_fixed";
0037 regulator-min-microvolt = <24000000>;
0038 regulator-max-microvolt = <24000000>;
0039 regulator-always-on;
0040 };
0041
0042 v5_0: fixedregulator-v5_0 {
0043 /* TPS54531 */
0044 compatible = "regulator-fixed";
0045 regulator-name = "v5_0_fixed";
0046 regulator-min-microvolt = <5000000>;
0047 regulator-max-microvolt = <5000000>;
0048 vin-supply = <&vmain>;
0049 regulator-always-on;
0050 };
0051
0052 vdd_3v3: fixedregulator-vdd_3v3 {
0053 /* TLV62084 */
0054 compatible = "regulator-fixed";
0055 regulator-name = "vdd_3v3_fixed";
0056 regulator-min-microvolt = <3300000>;
0057 regulator-max-microvolt = <3300000>;
0058 vin-supply = <&v5_0>;
0059 regulator-always-on;
0060 };
0061
0062 vdd_1v8: fixedregulator-vdd_1v8 {
0063 /* TLV62084 */
0064 compatible = "regulator-fixed";
0065 regulator-name = "vdd_1v8_fixed";
0066 regulator-min-microvolt = <1800000>;
0067 regulator-max-microvolt = <1800000>;
0068 vin-supply = <&v5_0>;
0069 regulator-always-on;
0070 };
0071
0072 vdds_ddr: fixedregulator-vdds_ddr {
0073 /* TLV62080 */
0074 compatible = "regulator-fixed";
0075 regulator-name = "vdds_ddr_fixed";
0076 regulator-min-microvolt = <1350000>;
0077 regulator-max-microvolt = <1350000>;
0078 vin-supply = <&v5_0>;
0079 regulator-always-on;
0080 };
0081
0082 vref_ddr: fixedregulator-vref_ddr {
0083 /* LP2996A */
0084 compatible = "regulator-fixed";
0085 regulator-name = "vref_ddr_fixed";
0086 regulator-min-microvolt = <675000>;
0087 regulator-max-microvolt = <675000>;
0088 vin-supply = <&vdd_3v3>;
0089 regulator-always-on;
0090 };
0091
0092 vtt_ddr: fixedregulator-vtt_ddr {
0093 /* LP2996A */
0094 compatible = "regulator-fixed";
0095 regulator-name = "vtt_ddr_fixed";
0096 regulator-min-microvolt = <675000>;
0097 regulator-max-microvolt = <675000>;
0098 vin-supply = <&vdd_3v3>;
0099 regulator-always-on;
0100 };
0101
0102 vdd_0v9: fixedregulator-vdd_0v9 {
0103 /* TPS62180 */
0104 compatible = "regulator-fixed";
0105 regulator-name = "vdd_0v9_fixed";
0106 regulator-min-microvolt = <900000>;
0107 regulator-max-microvolt = <900000>;
0108 vin-supply = <&v5_0>;
0109 regulator-always-on;
0110 };
0111
0112 vddb: fixedregulator-vddb {
0113 /* TPS22945 */
0114 compatible = "regulator-fixed";
0115 regulator-name = "vddb_fixed";
0116 regulator-min-microvolt = <3300000>;
0117 regulator-max-microvolt = <3300000>;
0118
0119 gpio = <&gpio1 53 GPIO_ACTIVE_HIGH>;
0120 enable-active-high;
0121 };
0122
0123 gpio-decoder {
0124 compatible = "gpio-decoder";
0125 gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>,
0126 <&pca9536 2 GPIO_ACTIVE_HIGH>,
0127 <&pca9536 1 GPIO_ACTIVE_HIGH>,
0128 <&pca9536 0 GPIO_ACTIVE_HIGH>;
0129 linux,axis = <0>; /* ABS_X */
0130 decoder-max-value = <9>;
0131 };
0132
0133 leds1 {
0134 compatible = "gpio-leds";
0135 pinctrl-names = "default";
0136 pinctrl-0 = <&user_leds>;
0137
0138 led0 {
0139 label = "status0:red:cpu0";
0140 gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
0141 default-state = "off";
0142 linux,default-trigger = "cpu0";
0143 };
0144
0145 led1 {
0146 label = "status0:green:usr";
0147 gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
0148 default-state = "off";
0149 };
0150
0151 led2 {
0152 label = "status0:yellow:usr";
0153 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
0154 default-state = "off";
0155 };
0156
0157 led3 {
0158 label = "status1:red:mmc0";
0159 gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
0160 default-state = "off";
0161 linux,default-trigger = "mmc0";
0162 };
0163
0164 led4 {
0165 label = "status1:green:usr";
0166 gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
0167 default-state = "off";
0168 };
0169
0170 led5 {
0171 label = "status1:yellow:usr";
0172 gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
0173 default-state = "off";
0174 };
0175
0176 led6 {
0177 label = "status2:red:usr";
0178 gpios = <&gpio0 44 GPIO_ACTIVE_HIGH>;
0179 default-state = "off";
0180 };
0181
0182 led7 {
0183 label = "status2:green:usr";
0184 gpios = <&gpio0 43 GPIO_ACTIVE_HIGH>;
0185 default-state = "off";
0186 };
0187
0188 led8 {
0189 label = "status2:yellow:usr";
0190 gpios = <&gpio0 42 GPIO_ACTIVE_HIGH>;
0191 default-state = "off";
0192 };
0193
0194 led9 {
0195 label = "status3:red:usr";
0196 gpios = <&gpio0 41 GPIO_ACTIVE_HIGH>;
0197 default-state = "off";
0198 };
0199
0200 led10 {
0201 label = "status3:green:usr";
0202 gpios = <&gpio0 101 GPIO_ACTIVE_HIGH>;
0203 default-state = "off";
0204 };
0205
0206 led11 {
0207 label = "status3:yellow:usr";
0208 gpios = <&gpio0 102 GPIO_ACTIVE_HIGH>;
0209 default-state = "off";
0210 };
0211
0212 led12 {
0213 label = "status4:green:heartbeat";
0214 gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
0215 linux,default-trigger = "heartbeat";
0216 };
0217 };
0218 };
0219
0220 &k2g_pinctrl {
0221 uart0_pins: pinmux_uart0_pins {
0222 pinctrl-single,pins = <
0223 K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0224 K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
0225 >;
0226 };
0227
0228 qspi_pins: pinmux_qspi_pins {
0229 pinctrl-single,pins = <
0230 K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
0231 K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
0232 K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
0233 K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
0234 K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
0235 K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
0236 K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
0237 >;
0238 };
0239
0240 mmc1_pins: pinmux_mmc1_pins {
0241 pinctrl-single,pins = <
0242 K2G_CORE_IOPAD(0x10FC) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
0243 K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
0244 K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
0245 K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
0246 K2G_CORE_IOPAD(0x110C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */
0247 K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
0248 K2G_CORE_IOPAD(0x1114) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc1_sdcd.gpio0_69 */
0249 K2G_CORE_IOPAD(0x1118) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_sdwp.mmc1_sdwp */
0250 K2G_CORE_IOPAD(0x111C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_pow.mmc1_pow */
0251 >;
0252 };
0253
0254 i2c0_pins: pinmux_i2c0_pins {
0255 pinctrl-single,pins = <
0256 K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
0257 K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0258 >;
0259 };
0260
0261 i2c1_pins: pinmux_i2c1_pins {
0262 pinctrl-single,pins = <
0263 K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */
0264 K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */
0265 >;
0266 };
0267
0268 user_leds: pinmux_user_leds {
0269 pinctrl-single,pins = <
0270 K2G_CORE_IOPAD(0x102c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad11.gpio0_11 */
0271 K2G_CORE_IOPAD(0x1030) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad12.gpio0_12 */
0272 K2G_CORE_IOPAD(0x1034) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad13.gpio0_13 */
0273 K2G_CORE_IOPAD(0x1038) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad14.gpio0_14 */
0274 K2G_CORE_IOPAD(0x103c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad15.gpio0_15 */
0275 K2G_CORE_IOPAD(0x1040) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_clk.gpio0_16 */
0276 K2G_CORE_IOPAD(0x104c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_wen.gpio0_19 */
0277 K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data9.gpio0_44 */
0278 K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data10.gpio0_43 */
0279 K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data11.gpio0_42 */
0280 K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data12.gpio0_41 */
0281 K2G_CORE_IOPAD(0x11b8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn0.gpio0_101 */
0282 K2G_CORE_IOPAD(0x11bc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn1.gpio0_102 */
0283 >;
0284 };
0285
0286 emac_pins: pinmux_emac_pins {
0287 pinctrl-single,pins = <
0288 K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */
0289 K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */
0290 K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */
0291 K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */
0292 K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */
0293 K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */
0294 K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */
0295 K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */
0296 K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */
0297 K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */
0298 K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */
0299 K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */
0300 >;
0301 };
0302
0303 mdio_pins: pinmux_mdio_pins {
0304 pinctrl-single,pins = <
0305 K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */
0306 K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */
0307 >;
0308 };
0309 };
0310
0311 &uart0 {
0312 pinctrl-names = "default";
0313 pinctrl-0 = <&uart0_pins>;
0314 status = "okay";
0315 };
0316
0317 &dsp0 {
0318 memory-region = <&dsp_common_memory>;
0319 status = "okay";
0320 };
0321
0322 &qspi {
0323 pinctrl-names = "default";
0324 pinctrl-0 = <&qspi_pins>;
0325 cdns,rclk-en;
0326 status = "okay";
0327
0328 flash0: flash@0 {
0329 compatible = "s25fl256s1", "jedec,spi-nor";
0330 reg = <0>;
0331 spi-tx-bus-width = <1>;
0332 spi-rx-bus-width = <4>;
0333 spi-max-frequency = <96000000>;
0334 #address-cells = <1>;
0335 #size-cells = <1>;
0336 cdns,read-delay = <5>;
0337 cdns,tshsl-ns = <500>;
0338 cdns,tsd2d-ns = <500>;
0339 cdns,tchsh-ns = <119>;
0340 cdns,tslch-ns = <119>;
0341
0342 partition@0 {
0343 label = "QSPI.u-boot";
0344 reg = <0x00000000 0x00100000>;
0345 };
0346 partition@1 {
0347 label = "QSPI.u-boot-env";
0348 reg = <0x00100000 0x00040000>;
0349 };
0350 partition@2 {
0351 label = "QSPI.skern";
0352 reg = <0x00140000 0x0040000>;
0353 };
0354 partition@3 {
0355 label = "QSPI.pmmc-firmware";
0356 reg = <0x00180000 0x0040000>;
0357 };
0358 partition@4 {
0359 label = "QSPI.kernel";
0360 reg = <0x001c0000 0x0800000>;
0361 };
0362 partition@5 {
0363 label = "QSPI.u-boot-spl-os";
0364 reg = <0x009c0000 0x0040000>;
0365 };
0366 partition@6 {
0367 label = "QSPI.file-system";
0368 reg = <0x00a00000 0x1600000>;
0369 };
0370 };
0371 };
0372
0373 &gpio0 {
0374 status = "okay";
0375 };
0376
0377 &gpio1 {
0378 status = "okay";
0379 };
0380
0381 &mmc1 {
0382 pinctrl-names = "default";
0383 pinctrl-0 = <&mmc1_pins>;
0384 vmmc-supply = <&vdd_3v3>;
0385 cd-gpios = <&gpio0 69 GPIO_ACTIVE_LOW>;
0386 status = "okay";
0387 };
0388
0389 &i2c0 {
0390 pinctrl-names = "default";
0391 pinctrl-0 = <&i2c0_pins>;
0392 status = "okay";
0393
0394 eeprom@50 {
0395 compatible = "atmel,24c256";
0396 reg = <0x50>;
0397 };
0398 };
0399
0400 &i2c1 {
0401 pinctrl-names = "default";
0402 pinctrl-0 = <&i2c1_pins>;
0403 status = "okay";
0404 clock-frequency = <400000>;
0405
0406 pca9536: gpio@41 {
0407 compatible = "ti,pca9536";
0408 reg = <0x41>;
0409 gpio-controller;
0410 #gpio-cells = <2>;
0411 vcc-supply = <&vdd_3v3>;
0412 };
0413 };
0414
0415 &qmss {
0416 status = "okay";
0417 };
0418
0419 &knav_dmas {
0420 status = "okay";
0421 };
0422
0423 &netcp {
0424 pinctrl-names = "default";
0425 pinctrl-0 = <&emac_pins>;
0426 status = "okay";
0427 };
0428
0429 &mdio {
0430 pinctrl-names = "default";
0431 pinctrl-0 = <&mdio_pins>;
0432 status = "okay";
0433 ethphy0: ethernet-phy@0 {
0434 reg = <0>;
0435 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
0436 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
0437 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
0438 ti,min-output-impedance;
0439 ti,dp83867-rxctrl-strap-quirk;
0440 };
0441 };
0442
0443 &gbe0 {
0444 phy-handle = <ðphy0>;
0445 phy-mode = "rgmii-id";
0446 status = "okay";
0447 };
