0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for K2G EVM
0004 *
0005 * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
0006 */
0007 /dts-v1/;
0008
0009 #include "keystone-k2g.dtsi"
0010
0011 / {
0012 compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone";
0013 model = "Texas Instruments K2G General Purpose EVM";
0014
0015 memory@800000000 {
0016 device_type = "memory";
0017 reg = <0x00000008 0x00000000 0x00000000 0x80000000>;
0018 };
0019
0020 reserved-memory {
0021 #address-cells = <2>;
0022 #size-cells = <2>;
0023 ranges;
0024
0025 dsp_common_memory: dsp-common-memory@81f800000 {
0026 compatible = "shared-dma-pool";
0027 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
0028 reusable;
0029 status = "okay";
0030 };
0031 };
0032
0033 vcc3v3_dcin_reg: fixedregulator-vcc3v3-dcin {
0034 compatible = "regulator-fixed";
0035 regulator-name = "mmc0_fixed";
0036 regulator-min-microvolt = <3300000>;
0037 regulator-max-microvolt = <3300000>;
0038 regulator-always-on;
0039 };
0040
0041 vcc1v8_ldo1_reg: fixedregulator-vcc1v8-ldo1 {
0042 compatible = "regulator-fixed";
0043 regulator-name = "ldo1";
0044 regulator-min-microvolt = <1800000>;
0045 regulator-max-microvolt = <1800000>;
0046 regulator-always-on;
0047 };
0048
0049 vcc1v8_ldo2_reg: fixedregulator-vcc1v8-ldo2 {
0050 compatible = "regulator-fixed";
0051 regulator-name = "ldo2";
0052 regulator-min-microvolt = <1800000>;
0053 regulator-max-microvolt = <1800000>;
0054 regulator-always-on;
0055 };
0056
0057 hdmi: connector {
0058 compatible = "hdmi-connector";
0059 label = "hdmi";
0060
0061 type = "a";
0062
0063 port {
0064 hdmi_connector_in: endpoint {
0065 remote-endpoint = <&sii9022_out>;
0066 };
0067 };
0068 };
0069
0070 aud_mclk: aud_mclk {
0071 compatible = "fixed-clock";
0072 #clock-cells = <0>;
0073 clock-frequency = <12288000>;
0074 };
0075
0076 sound0: sound@0 {
0077 compatible = "simple-audio-card";
0078 simple-audio-card,name = "K2G-EVM";
0079 simple-audio-card,widgets =
0080 "Headphone", "Headphone Jack",
0081 "Line", "Line In";
0082 simple-audio-card,routing =
0083 "Headphone Jack", "HPLOUT",
0084 "Headphone Jack", "HPROUT",
0085 "LINE1L", "Line In",
0086 "LINE1R", "Line In";
0087
0088 simple-audio-card,dai-link@0 {
0089 format = "i2s";
0090 bitclock-master = <&sound0_0_master>;
0091 frame-master = <&sound0_0_master>;
0092 sound0_0_master: cpu {
0093 sound-dai = <&mcasp2>;
0094 clocks = <&k2g_clks 0x6 1>;
0095 system-clock-direction-out;
0096 };
0097
0098 codec {
0099 sound-dai = <&tlv320aic3106>;
0100 clocks = <&aud_mclk>;
0101 };
0102 };
0103
0104 simple-audio-card,dai-link@1 {
0105 format = "i2s";
0106 bitclock-master = <&sound0_1_master>;
0107 frame-master = <&sound0_1_master>;
0108 sound0_1_master: cpu {
0109 sound-dai = <&mcasp2>;
0110 clocks = <&k2g_clks 0x6 1>;
0111 system-clock-direction-out;
0112 };
0113
0114 codec {
0115 sound-dai = <&sii9022>;
0116 clocks = <&aud_mclk>;
0117 };
0118 };
0119 };
0120 };
0121
0122 &k2g_pinctrl {
0123 uart0_pins: pinmux_uart0_pins {
0124 pinctrl-single,pins = <
0125 K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0126 K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
0127 >;
0128 };
0129
0130 mmc0_pins: pinmux_mmc0_pins {
0131 pinctrl-single,pins = <
0132 K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */
0133 K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat2.mmc0_dat2 */
0134 K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat1.mmc0_dat1 */
0135 K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat0.mmc0_dat0 */
0136 K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_clk.mmc0_clk */
0137 K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_cmd.mmc0_cmd */
0138 K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc0_sdcd.gpio1_12 */
0139 >;
0140 };
0141
0142 mmc1_pins: pinmux_mmc1_pins {
0143 pinctrl-single,pins = <
0144 K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat7.mmc1_dat7 */
0145 K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat6.mmc1_dat6 */
0146 K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat5.mmc1_dat5 */
0147 K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat4.mmc1_dat4 */
0148 K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
0149 K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
0150 K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
0151 K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
0152 K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */
0153 K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
0154 >;
0155 };
0156
0157 i2c0_pins: pinmux_i2c0_pins {
0158 pinctrl-single,pins = <
0159 K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
0160 K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0161 >;
0162 };
0163
0164 i2c1_pins: pinmux_i2c1_pins {
0165 pinctrl-single,pins = <
0166 K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */
0167 K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */
0168 >;
0169 };
0170
0171 ecap0_pins: ecap0_pins {
0172 pinctrl-single,pins = <
0173 K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */
0174 >;
0175 };
0176
0177 spi1_pins: pinmux_spi1_pins {
0178 pinctrl-single,pins = <
0179 K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_scs0.spi1_scs0 */
0180 K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_clk.spi1_clk */
0181 K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_miso.spi1_miso */
0182 K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_mosi.spi1_mosi */
0183 >;
0184 };
0185
0186 qspi_pins: pinmux_qspi_pins {
0187 pinctrl-single,pins = <
0188 K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
0189 K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
0190 K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
0191 K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
0192 K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
0193 K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
0194 K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
0195 >;
0196 };
0197
0198 uart2_pins: pinmux_uart2_pins {
0199 pinctrl-single,pins = <
0200 K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart2_rxd.uart2_rxd */
0201 K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart2_txd.uart2_txd */
0202 >;
0203 };
0204
0205 dcan0_pins: pinmux_dcan0_pins {
0206 pinctrl-single,pins = <
0207 K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dcan0tx.dcan0tx */
0208 K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* dcan0rx.dcan0rx */
0209 >;
0210 };
0211
0212 dcan1_pins: pinmux_dcan1_pins {
0213 pinctrl-single,pins = <
0214 K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* qspicsn2.dcan1tx */
0215 K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3.dcan1rx */
0216 >;
0217 };
0218
0219 emac_pins: pinmux_emac_pins {
0220 pinctrl-single,pins = <
0221 K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */
0222 K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */
0223 K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */
0224 K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */
0225 K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */
0226 K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */
0227 K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */
0228 K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */
0229 K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */
0230 K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */
0231 K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */
0232 K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */
0233 >;
0234 };
0235
0236 mdio_pins: pinmux_mdio_pins {
0237 pinctrl-single,pins = <
0238 K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */
0239 K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */
0240 >;
0241 };
0242
0243 vout_pins: pinmux_vout_pins {
0244 pinctrl-single,pins = <
0245 K2G_CORE_IOPAD(0x1078) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata23.dssdata23 */
0246 K2G_CORE_IOPAD(0x107c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata22.dssdata22 */
0247 K2G_CORE_IOPAD(0x1080) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata21.dssdata21 */
0248 K2G_CORE_IOPAD(0x1084) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata20.dssdata20 */
0249 K2G_CORE_IOPAD(0x1088) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata19.dssdata19 */
0250 K2G_CORE_IOPAD(0x108c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata18.dssdata18 */
0251 K2G_CORE_IOPAD(0x1090) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata17.dssdata17 */
0252 K2G_CORE_IOPAD(0x1094) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata16.dssdata16 */
0253 K2G_CORE_IOPAD(0x1098) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata15.dssdata15 */
0254 K2G_CORE_IOPAD(0x109c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata14.dssdata14 */
0255 K2G_CORE_IOPAD(0x10a0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata13.dssdata13 */
0256 K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata12.dssdata12 */
0257 K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata11.dssdata11 */
0258 K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata10.dssdata10 */
0259 K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata9.dssdata9 */
0260 K2G_CORE_IOPAD(0x10b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata8.dssdata8 */
0261 K2G_CORE_IOPAD(0x10b8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata7.dssdata7 */
0262 K2G_CORE_IOPAD(0x10bc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata6.dssdata6 */
0263 K2G_CORE_IOPAD(0x10c0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata5.dssdata5 */
0264 K2G_CORE_IOPAD(0x10c4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata4.dssdata4 */
0265 K2G_CORE_IOPAD(0x10c8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata3.dssdata3 */
0266 K2G_CORE_IOPAD(0x10cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata2.dssdata2 */
0267 K2G_CORE_IOPAD(0x10d0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata1.dssdata1 */
0268 K2G_CORE_IOPAD(0x10d4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata0.dssdata0 */
0269 K2G_CORE_IOPAD(0x10d8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssvsync.dssvsync */
0270 K2G_CORE_IOPAD(0x10dc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsshsync.dsshsync */
0271 K2G_CORE_IOPAD(0x10e0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsspclk.dsspclk */
0272 K2G_CORE_IOPAD(0x10e4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssde.dssde */
0273 K2G_CORE_IOPAD(0x10e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssfid.dssfid */
0274 >;
0275 };
0276
0277 mcasp2_pins: pinmux_mcasp2_pins {
0278 pinctrl-single,pins = <
0279 K2G_CORE_IOPAD(0x1234) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo2.mcasp2_axr2 */
0280 K2G_CORE_IOPAD(0x1238) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo3.mcasp2_axr3 */
0281 K2G_CORE_IOPAD(0x1254) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo10.mcasp2_afsx */
0282 K2G_CORE_IOPAD(0x125c) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo12.mcasp2_aclkx */
0283 >;
0284 };
0285 };
0286
0287 &uart0 {
0288 pinctrl-names = "default";
0289 pinctrl-0 = <&uart0_pins>;
0290 status = "okay";
0291 };
0292
0293 &gpio1 {
0294 status = "okay";
0295 };
0296
0297 &mmc0 {
0298 pinctrl-names = "default";
0299 pinctrl-0 = <&mmc0_pins>;
0300 vmmc-supply = <&vcc3v3_dcin_reg>;
0301 vqmmc-supply = <&vcc3v3_dcin_reg>;
0302 cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
0303 status = "okay";
0304 };
0305
0306 &mmc1 {
0307 pinctrl-names = "default";
0308 pinctrl-0 = <&mmc1_pins>;
0309 vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */
0310 vqmmc-supply = <&vcc1v8_ldo1_reg>;
0311 ti,non-removable;
0312 status = "okay";
0313 };
0314
0315 &dsp0 {
0316 memory-region = <&dsp_common_memory>;
0317 status = "okay";
0318 };
0319
0320 &i2c0 {
0321 pinctrl-names = "default";
0322 pinctrl-0 = <&i2c0_pins>;
0323 status = "okay";
0324
0325 eeprom@50 {
0326 compatible = "atmel,24c1024";
0327 reg = <0x50>;
0328 };
0329 };
0330
0331 &keystone_usb0 {
0332 status = "okay";
0333 };
0334
0335 &usb0_phy {
0336 status = "okay";
0337 };
0338
0339 &usb0 {
0340 dr_mode = "host";
0341 status = "okay";
0342 };
0343
0344 &keystone_usb1 {
0345 status = "okay";
0346 };
0347
0348 &usb1_phy {
0349 status = "okay";
0350 };
0351
0352 &usb1 {
0353 dr_mode = "peripheral";
0354 status = "okay";
0355 };
0356
0357 &ecap0 {
0358 status = "okay";
0359 pinctrl-names = "default";
0360 pinctrl-0 = <&ecap0_pins>;
0361 };
0362
0363 &spi1 {
0364 pinctrl-names = "default";
0365 pinctrl-0 = <&spi1_pins>;
0366 status = "okay";
0367
0368 spi_nor: flash@0 {
0369 #address-cells = <1>;
0370 #size-cells = <1>;
0371 compatible = "jedec,spi-nor";
0372 spi-max-frequency = <5000000>;
0373 m25p,fast-read;
0374 reg = <0>;
0375
0376 partition@0 {
0377 label = "u-boot-spl";
0378 reg = <0x0 0x100000>;
0379 read-only;
0380 };
0381
0382 partition@1 {
0383 label = "misc";
0384 reg = <0x100000 0xf00000>;
0385 };
0386 };
0387 };
0388
0389 &qspi {
0390 status = "okay";
0391 pinctrl-names = "default";
0392 pinctrl-0 = <&qspi_pins>;
0393 cdns,rclk-en;
0394
0395 flash0: flash@0 {
0396 compatible = "s25fl512s", "jedec,spi-nor";
0397 reg = <0>;
0398 spi-tx-bus-width = <1>;
0399 spi-rx-bus-width = <4>;
0400 spi-max-frequency = <96000000>;
0401 #address-cells = <1>;
0402 #size-cells = <1>;
0403 cdns,read-delay = <5>;
0404 cdns,tshsl-ns = <500>;
0405 cdns,tsd2d-ns = <500>;
0406 cdns,tchsh-ns = <119>;
0407 cdns,tslch-ns = <119>;
0408
0409 partition@0 {
0410 label = "QSPI.u-boot-spl-os";
0411 reg = <0x00000000 0x00100000>;
0412 };
0413 partition@1 {
0414 label = "QSPI.u-boot-env";
0415 reg = <0x00100000 0x00040000>;
0416 };
0417 partition@2 {
0418 label = "QSPI.skern";
0419 reg = <0x00140000 0x0040000>;
0420 };
0421 partition@3 {
0422 label = "QSPI.pmmc-firmware";
0423 reg = <0x00180000 0x0040000>;
0424 };
0425 partition@4 {
0426 label = "QSPI.kernel";
0427 reg = <0x001C0000 0x0800000>;
0428 };
0429 partition@5 {
0430 label = "QSPI.file-system";
0431 reg = <0x009C0000 0x3640000>;
0432 };
0433 };
0434 };
0435
0436 &uart2 {
0437 pinctrl-names = "default";
0438 pinctrl-0 = <&uart2_pins>;
0439 status = "okay";
0440 };
0441
0442 &dcan0 {
0443 pinctrl-names = "default";
0444 pinctrl-0 = <&dcan0_pins>;
0445 status = "okay";
0446 };
0447
0448 &dcan1 {
0449 pinctrl-names = "default";
0450 pinctrl-0 = <&dcan1_pins>;
0451 status = "okay";
0452 };
0453
0454 &qmss {
0455 status = "okay";
0456 };
0457
0458 &knav_dmas {
0459 status = "okay";
0460 };
0461
0462 &mdio {
0463 pinctrl-names = "default";
0464 pinctrl-0 = <&mdio_pins>;
0465 status = "okay";
0466 ethphy0: ethernet-phy@0 {
0467 reg = <0>;
0468 };
0469 };
0470
0471 &gbe0 {
0472 phy-handle = <ðphy0>;
0473 phy-mode = "rgmii-rxid";
0474 status = "okay";
0475 };
0476
0477 &netcp {
0478 pinctrl-names = "default";
0479 pinctrl-0 = <&emac_pins>;
0480 status = "okay";
0481 };
0482
0483 &i2c1 {
0484 pinctrl-names = "default";
0485 pinctrl-0 = <&i2c1_pins>;
0486 status = "okay";
0487 clock-frequency = <400000>;
0488
0489 sii9022: sii9022@3b {
0490 #sound-dai-cells = <0>;
0491 compatible = "sil,sii9022";
0492 reg = <0x3b>;
0493
0494 sil,i2s-data-lanes = < 0 >;
0495 clocks = <&aud_mclk>;
0496 clock-names = "mclk";
0497
0498 ports {
0499 #address-cells = <1>;
0500 #size-cells = <0>;
0501
0502 port@0 {
0503 reg = <0>;
0504
0505 sii9022_in: endpoint {
0506 remote-endpoint = <&dpi_out>;
0507 };
0508 };
0509
0510 port@1 {
0511 reg = <1>;
0512
0513 sii9022_out: endpoint {
0514 remote-endpoint = <&hdmi_connector_in>;
0515 };
0516 };
0517 };
0518 };
0519
0520 tlv320aic3106: tlv320aic3106@1b {
0521 #sound-dai-cells = <0>;
0522 compatible = "ti,tlv320aic3106";
0523 reg = <0x1b>;
0524 status = "okay";
0525
0526 /* Regulators */
0527 AVDD-supply = <&vcc3v3_dcin_reg>;
0528 IOVDD-supply = <&vcc3v3_dcin_reg>;
0529 DRVDD-supply = <&vcc3v3_dcin_reg>;
0530 DVDD-supply = <&vcc1v8_ldo2_reg>;
0531 };
0532 };
0533
0534 &dss {
0535 pinctrl-names = "default";
0536 pinctrl-0 = <&vout_pins>;
0537 status = "ok";
0538
0539 port {
0540 dpi_out: endpoint {
0541 remote-endpoint = <&sii9022_in>;
0542 data-lines = <24>;
0543 };
0544 };
0545 };
0546
0547 &mcasp2 {
0548 #sound-dai-cells = <0>;
0549
0550 pinctrl-names = "default";
0551 pinctrl-0 = <&mcasp2_pins>;
0552
0553 assigned-clocks = <&k2g_clks 0x4c 2>, <&k2g_clks 0x6 1>;
0554 assigned-clock-parents = <0>, <&k2g_clks 0x6 2>;
0555 assigned-clock-rates = <22579200>, <0>;
0556
0557 status = "okay";
0558
0559 op-mode = <0>; /* MCASP_IIS_MODE */
0560 tdm-slots = <2>;
0561 /* 6 serializer */
0562 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
0563 0 0 1 2 0 0 // AXR2: TX, AXR3: rx
0564 >;
0565 tx-num-evt = <32>;
0566 rx-num-evt = <32>;
0567 };
