0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Keystone 2 Edison SoC specific device tree
0004 *
0005 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
0006 */
0007
0008 clocks {
0009 mainpllclk: mainpllclk@2310110 {
0010 #clock-cells = <0>;
0011 compatible = "ti,keystone,main-pll-clock";
0012 clocks = <&refclksys>;
0013 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
0014 reg-names = "control", "multiplier", "post-divider";
0015 };
0016
0017 papllclk: papllclk@2620358 {
0018 #clock-cells = <0>;
0019 compatible = "ti,keystone,pll-clock";
0020 clocks = <&refclkpass>;
0021 clock-output-names = "papllclk";
0022 reg = <0x02620358 4>;
0023 reg-names = "control";
0024 };
0025
0026 ddr3apllclk: ddr3apllclk@2620360 {
0027 #clock-cells = <0>;
0028 compatible = "ti,keystone,pll-clock";
0029 clocks = <&refclkddr3a>;
0030 clock-output-names = "ddr-3a-pll-clk";
0031 reg = <0x02620360 4>;
0032 reg-names = "control";
0033 };
0034
0035 clkusb1: clkusb1@2350004 {
0036 #clock-cells = <0>;
0037 compatible = "ti,keystone,psc-clock";
0038 clocks = <&chipclk16>;
0039 clock-output-names = "usb1";
0040 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
0041 reg-names = "control", "domain";
0042 domain-id = <0>;
0043 };
0044
0045 clkhyperlink0: clkhyperlink0@2350030 {
0046 #clock-cells = <0>;
0047 compatible = "ti,keystone,psc-clock";
0048 clocks = <&chipclk12>;
0049 clock-output-names = "hyperlink-0";
0050 reg = <0x02350030 0xb00>, <0x02350014 0x400>;
0051 reg-names = "control", "domain";
0052 domain-id = <5>;
0053 };
0054
0055 clkpcie1: clkpcie1@235006c {
0056 #clock-cells = <0>;
0057 compatible = "ti,keystone,psc-clock";
0058 clocks = <&chipclk12>;
0059 clock-output-names = "pcie1";
0060 reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
0061 reg-names = "control", "domain";
0062 domain-id = <18>;
0063 };
0064
0065 clkxge: clkxge@23500c8 {
0066 #clock-cells = <0>;
0067 compatible = "ti,keystone,psc-clock";
0068 clocks = <&chipclk13>;
0069 clock-output-names = "xge";
0070 reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
0071 reg-names = "control", "domain";
0072 domain-id = <29>;
0073 };
0074
0075 /*
0076 * Below are set of fixed, input clocks definitions,
0077 * for which real frequencies have to be defined in board files.
0078 * Those clocks can be used as reference clocks for some HW modules
0079 * (as cpts, for example) by configuring corresponding clock muxes.
0080 */
0081 tsipclka: tsipclka {
0082 #clock-cells = <0>;
0083 compatible = "fixed-clock";
0084 clock-frequency = <0>;
0085 clock-output-names = "tsipclka";
0086 };
0087
0088 tsipclkb: tsipclkb {
0089 #clock-cells = <0>;
0090 compatible = "fixed-clock";
0091 clock-frequency = <0>;
0092 clock-output-names = "tsipclkb";
0093 };
0094 };
