0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for Keystone 2 clock tree
0004 *
0005 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
0006 */
0007
0008 clocks {
0009 #address-cells = <1>;
0010 #size-cells = <1>;
0011 ranges;
0012
0013 mainmuxclk: mainmuxclk@2310108 {
0014 #clock-cells = <0>;
0015 compatible = "ti,keystone,pll-mux-clock";
0016 clocks = <&mainpllclk>, <&refclksys>;
0017 reg = <0x02310108 4>;
0018 bit-shift = <23>;
0019 bit-mask = <1>;
0020 clock-output-names = "mainmuxclk";
0021 };
0022
0023 chipclk1: chipclk1 {
0024 #clock-cells = <0>;
0025 compatible = "fixed-factor-clock";
0026 clocks = <&mainmuxclk>;
0027 clock-div = <1>;
0028 clock-mult = <1>;
0029 clock-output-names = "chipclk1";
0030 };
0031
0032 chipclk1rstiso: chipclk1rstiso {
0033 #clock-cells = <0>;
0034 compatible = "fixed-factor-clock";
0035 clocks = <&mainmuxclk>;
0036 clock-div = <1>;
0037 clock-mult = <1>;
0038 clock-output-names = "chipclk1rstiso";
0039 };
0040
0041 gemtraceclk: gemtraceclk@2310120 {
0042 #clock-cells = <0>;
0043 compatible = "ti,keystone,pll-divider-clock";
0044 clocks = <&mainmuxclk>;
0045 reg = <0x02310120 4>;
0046 bit-shift = <0>;
0047 bit-mask = <8>;
0048 clock-output-names = "gemtraceclk";
0049 };
0050
0051 chipstmxptclk: chipstmxptclk@2310164 {
0052 #clock-cells = <0>;
0053 compatible = "ti,keystone,pll-divider-clock";
0054 clocks = <&mainmuxclk>;
0055 reg = <0x02310164 4>;
0056 bit-shift = <0>;
0057 bit-mask = <8>;
0058 clock-output-names = "chipstmxptclk";
0059 };
0060
0061 chipclk12: chipclk12 {
0062 #clock-cells = <0>;
0063 compatible = "fixed-factor-clock";
0064 clocks = <&chipclk1>;
0065 clock-div = <2>;
0066 clock-mult = <1>;
0067 clock-output-names = "chipclk12";
0068 };
0069
0070 chipclk13: chipclk13 {
0071 #clock-cells = <0>;
0072 compatible = "fixed-factor-clock";
0073 clocks = <&chipclk1>;
0074 clock-div = <3>;
0075 clock-mult = <1>;
0076 clock-output-names = "chipclk13";
0077 };
0078
0079 paclk13: paclk13 {
0080 #clock-cells = <0>;
0081 compatible = "fixed-factor-clock";
0082 clocks = <&papllclk>;
0083 clock-div = <3>;
0084 clock-mult = <1>;
0085 clock-output-names = "paclk13";
0086 };
0087
0088 chipclk14: chipclk14 {
0089 #clock-cells = <0>;
0090 compatible = "fixed-factor-clock";
0091 clocks = <&chipclk1>;
0092 clock-div = <4>;
0093 clock-mult = <1>;
0094 clock-output-names = "chipclk14";
0095 };
0096
0097 chipclk16: chipclk16 {
0098 #clock-cells = <0>;
0099 compatible = "fixed-factor-clock";
0100 clocks = <&chipclk1>;
0101 clock-div = <6>;
0102 clock-mult = <1>;
0103 clock-output-names = "chipclk16";
0104 };
0105
0106 chipclk112: chipclk112 {
0107 #clock-cells = <0>;
0108 compatible = "fixed-factor-clock";
0109 clocks = <&chipclk1>;
0110 clock-div = <12>;
0111 clock-mult = <1>;
0112 clock-output-names = "chipclk112";
0113 };
0114
0115 chipclk124: chipclk124 {
0116 #clock-cells = <0>;
0117 compatible = "fixed-factor-clock";
0118 clocks = <&chipclk1>;
0119 clock-div = <24>;
0120 clock-mult = <1>;
0121 clock-output-names = "chipclk114";
0122 };
0123
0124 chipclk1rstiso13: chipclk1rstiso13 {
0125 #clock-cells = <0>;
0126 compatible = "fixed-factor-clock";
0127 clocks = <&chipclk1rstiso>;
0128 clock-div = <3>;
0129 clock-mult = <1>;
0130 clock-output-names = "chipclk1rstiso13";
0131 };
0132
0133 chipclk1rstiso14: chipclk1rstiso14 {
0134 #clock-cells = <0>;
0135 compatible = "fixed-factor-clock";
0136 clocks = <&chipclk1rstiso>;
0137 clock-div = <4>;
0138 clock-mult = <1>;
0139 clock-output-names = "chipclk1rstiso14";
0140 };
0141
0142 chipclk1rstiso16: chipclk1rstiso16 {
0143 #clock-cells = <0>;
0144 compatible = "fixed-factor-clock";
0145 clocks = <&chipclk1rstiso>;
0146 clock-div = <6>;
0147 clock-mult = <1>;
0148 clock-output-names = "chipclk1rstiso16";
0149 };
0150
0151 chipclk1rstiso112: chipclk1rstiso112 {
0152 #clock-cells = <0>;
0153 compatible = "fixed-factor-clock";
0154 clocks = <&chipclk1rstiso>;
0155 clock-div = <12>;
0156 clock-mult = <1>;
0157 clock-output-names = "chipclk1rstiso112";
0158 };
0159
0160 clkmodrst0: clkmodrst0@2350000 {
0161 #clock-cells = <0>;
0162 compatible = "ti,keystone,psc-clock";
0163 clocks = <&chipclk16>;
0164 clock-output-names = "modrst0";
0165 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
0166 reg-names = "control", "domain";
0167 domain-id = <0>;
0168 };
0169
0170
0171 clkusb: clkusb@2350008 {
0172 #clock-cells = <0>;
0173 compatible = "ti,keystone,psc-clock";
0174 clocks = <&chipclk16>;
0175 clock-output-names = "usb";
0176 reg = <0x02350008 0xb00>, <0x02350000 0x400>;
0177 reg-names = "control", "domain";
0178 domain-id = <0>;
0179 };
0180
0181 clkaemifspi: clkaemifspi@235000c {
0182 #clock-cells = <0>;
0183 compatible = "ti,keystone,psc-clock";
0184 clocks = <&chipclk16>;
0185 clock-output-names = "aemif-spi";
0186 reg = <0x0235000c 0xb00>, <0x02350000 0x400>;
0187 reg-names = "control", "domain";
0188 domain-id = <0>;
0189 };
0190
0191
0192 clkdebugsstrc: clkdebugsstrc@2350014 {
0193 #clock-cells = <0>;
0194 compatible = "ti,keystone,psc-clock";
0195 clocks = <&chipclk13>;
0196 clock-output-names = "debugss-trc";
0197 reg = <0x02350014 0xb00>, <0x02350000 0x400>;
0198 reg-names = "control", "domain";
0199 domain-id = <1>;
0200 };
0201
0202 clktetbtrc: clktetbtrc@2350018 {
0203 #clock-cells = <0>;
0204 compatible = "ti,keystone,psc-clock";
0205 clocks = <&chipclk13>;
0206 clock-output-names = "tetb-trc";
0207 reg = <0x02350018 0xb00>, <0x02350004 0x400>;
0208 reg-names = "control", "domain";
0209 domain-id = <1>;
0210 };
0211
0212 clkpa: clkpa@235001c {
0213 #clock-cells = <0>;
0214 compatible = "ti,keystone,psc-clock";
0215 clocks = <&paclk13>;
0216 clock-output-names = "pa";
0217 reg = <0x0235001c 0xb00>, <0x02350008 0x400>;
0218 reg-names = "control", "domain";
0219 domain-id = <2>;
0220 };
0221
0222 clkcpgmac: clkcpgmac@2350020 {
0223 #clock-cells = <0>;
0224 compatible = "ti,keystone,psc-clock";
0225 clocks = <&clkpa>;
0226 clock-output-names = "cpgmac";
0227 reg = <0x02350020 0xb00>, <0x02350008 0x400>;
0228 reg-names = "control", "domain";
0229 domain-id = <2>;
0230 };
0231
0232 clksa: clksa@2350024 {
0233 #clock-cells = <0>;
0234 compatible = "ti,keystone,psc-clock";
0235 clocks = <&clkpa>;
0236 clock-output-names = "sa";
0237 reg = <0x02350024 0xb00>, <0x02350008 0x400>;
0238 reg-names = "control", "domain";
0239 domain-id = <2>;
0240 };
0241
0242 clkpcie: clkpcie@2350028 {
0243 #clock-cells = <0>;
0244 compatible = "ti,keystone,psc-clock";
0245 clocks = <&chipclk12>;
0246 clock-output-names = "pcie";
0247 reg = <0x02350028 0xb00>, <0x0235000c 0x400>;
0248 reg-names = "control", "domain";
0249 domain-id = <3>;
0250 };
0251
0252 clksr: clksr@2350034 {
0253 #clock-cells = <0>;
0254 compatible = "ti,keystone,psc-clock";
0255 clocks = <&chipclk1rstiso112>;
0256 clock-output-names = "sr";
0257 reg = <0x02350034 0xb00>, <0x02350018 0x400>;
0258 reg-names = "control", "domain";
0259 domain-id = <6>;
0260 };
0261
0262 clkgem0: clkgem0@235003c {
0263 #clock-cells = <0>;
0264 compatible = "ti,keystone,psc-clock";
0265 clocks = <&chipclk1>;
0266 clock-output-names = "gem0";
0267 reg = <0x0235003c 0xb00>, <0x02350020 0x400>;
0268 reg-names = "control", "domain";
0269 domain-id = <8>;
0270 };
0271
0272 clkddr30: clkddr30@235005c {
0273 #clock-cells = <0>;
0274 compatible = "ti,keystone,psc-clock";
0275 clocks = <&chipclk12>;
0276 clock-output-names = "ddr3-0";
0277 reg = <0x0235005c 0xb00>, <0x02350040 0x400>;
0278 reg-names = "control", "domain";
0279 domain-id = <16>;
0280 };
0281
0282 clkwdtimer0: clkwdtimer0@2350000 {
0283 #clock-cells = <0>;
0284 compatible = "ti,keystone,psc-clock";
0285 clocks = <&clkmodrst0>;
0286 clock-output-names = "timer0";
0287 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
0288 reg-names = "control", "domain";
0289 domain-id = <0>;
0290 };
0291
0292 clkwdtimer1: clkwdtimer1@2350000 {
0293 #clock-cells = <0>;
0294 compatible = "ti,keystone,psc-clock";
0295 clocks = <&clkmodrst0>;
0296 clock-output-names = "timer1";
0297 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
0298 reg-names = "control", "domain";
0299 domain-id = <0>;
0300 };
0301
0302 clkwdtimer2: clkwdtimer2@2350000 {
0303 #clock-cells = <0>;
0304 compatible = "ti,keystone,psc-clock";
0305 clocks = <&clkmodrst0>;
0306 clock-output-names = "timer2";
0307 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
0308 reg-names = "control", "domain";
0309 domain-id = <0>;
0310 };
0311
0312 clkwdtimer3: clkwdtimer3@2350000 {
0313 #clock-cells = <0>;
0314 compatible = "ti,keystone,psc-clock";
0315 clocks = <&clkmodrst0>;
0316 clock-output-names = "timer3";
0317 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
0318 reg-names = "control", "domain";
0319 domain-id = <0>;
0320 };
0321
0322 clktimer15: clktimer15@2350000 {
0323 #clock-cells = <0>;
0324 compatible = "ti,keystone,psc-clock";
0325 clocks = <&clkmodrst0>;
0326 clock-output-names = "timer15";
0327 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
0328 reg-names = "control", "domain";
0329 domain-id = <0>;
0330 };
0331
0332 clkuart0: clkuart0@2350000 {
0333 #clock-cells = <0>;
0334 compatible = "ti,keystone,psc-clock";
0335 clocks = <&clkmodrst0>;
0336 clock-output-names = "uart0";
0337 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
0338 reg-names = "control", "domain";
0339 domain-id = <0>;
0340 };
0341
0342 clkuart1: clkuart1@2350000 {
0343 #clock-cells = <0>;
0344 compatible = "ti,keystone,psc-clock";
0345 clocks = <&clkmodrst0>;
0346 clock-output-names = "uart1";
0347 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
0348 reg-names = "control", "domain";
0349 domain-id = <0>;
0350 };
0351
0352 clkaemif: clkaemif@2350000 {
0353 #clock-cells = <0>;
0354 compatible = "ti,keystone,psc-clock";
0355 clocks = <&clkaemifspi>;
0356 clock-output-names = "aemif";
0357 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
0358 reg-names = "control", "domain";
0359 domain-id = <0>;
0360 };
0361
0362 clkusim: clkusim@2350000 {
0363 #clock-cells = <0>;
0364 compatible = "ti,keystone,psc-clock";
0365 clocks = <&clkmodrst0>;
0366 clock-output-names = "usim";
0367 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
0368 reg-names = "control", "domain";
0369 domain-id = <0>;
0370 };
0371
0372 clki2c: clki2c@2350000 {
0373 #clock-cells = <0>;
0374 compatible = "ti,keystone,psc-clock";
0375 clocks = <&clkmodrst0>;
0376 clock-output-names = "i2c";
0377 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
0378 reg-names = "control", "domain";
0379 domain-id = <0>;
0380 };
0381
0382 clkspi: clkspi@2350000 {
0383 #clock-cells = <0>;
0384 compatible = "ti,keystone,psc-clock";
0385 clocks = <&clkaemifspi>;
0386 clock-output-names = "spi";
0387 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
0388 reg-names = "control", "domain";
0389 domain-id = <0>;
0390 };
0391
0392 clkgpio: clkgpio@2350000 {
0393 #clock-cells = <0>;
0394 compatible = "ti,keystone,psc-clock";
0395 clocks = <&clkmodrst0>;
0396 clock-output-names = "gpio";
0397 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
0398 reg-names = "control", "domain";
0399 domain-id = <0>;
0400 };
0401
0402 clkkeymgr: clkkeymgr@2350000 {
0403 #clock-cells = <0>;
0404 compatible = "ti,keystone,psc-clock";
0405 clocks = <&clkmodrst0>;
0406 clock-output-names = "keymgr";
0407 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
0408 reg-names = "control", "domain";
0409 domain-id = <0>;
0410 };
0411
0412 /*
0413 * Below are set of fixed, input clocks definitions,
0414 * for which real frequencies have to be defined in board files.
0415 * Those clocks can be used as reference clocks for some HW modules
0416 * (as cpts, for example) by configuring corresponding clock muxes.
0417 */
0418 timi0: timi0 {
0419 #clock-cells = <0>;
0420 compatible = "fixed-clock";
0421 clock-frequency = <0>;
0422 clock-output-names = "timi0";
0423 };
0424
0425 timi1: timi1 {
0426 #clock-cells = <0>;
0427 compatible = "fixed-clock";
0428 clock-frequency = <0>;
0429 clock-output-names = "timi1";
0430 };
0431
0432 tsrefclk: tsrefclk {
0433 #clock-cells = <0>;
0434 compatible = "fixed-clock";
0435 clock-frequency = <0>;
0436 clock-output-names = "tsrefclk";
0437 };
0438 };
